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1. 发明公开

EP0501580A1 Sigma-delta modulator 失效
标题翻译： Σ-Deltamodulator。
公开(公告)号：EP0501580A1
公开(公告)日：1992-09-02
申请号：EP92200522.8
申请日：1992-02-24
申请人： Philips Electronics N.V.
发明人： Naus, Peter Johannes Anna , Dijkmans, Eise Carel , Nuijten, Petrus Antonius Cornelius Maria
IPC分类号： H03M3/00 , H03M7/30
CPC分类号： H03M7/3035 , H03M3/43 , H03M3/444 , H03M3/452 , H03M7/3028 , H03M7/3037
摘要： Sigma-delta modulator comprising a low-pass filter of the Nth order, which is constituted by a series combination of N first-order integrating sections (6.1, 6.2, 6.3, ..., 6.N) comprising each an integrator (12.1, 12.2, 12.3, ..., 12.N) and a limiter (14.1, 14.2, 14.3, ..., 14.N). The individual output signals of the sections are weighted by means of corresponding weighting amplifiers (16.1, 16.2, 16.3, ..., 16.N) and added together in an adder stage (18). The gains of the sections and the limiting values of the limiters are selected so that the last limiter (14.N) in the series arrangement is activated first when the signal level in the sigma-delta modulator increases, subsequently the last-but-one limiter, and so on. This reduces the order of the filter system each time by one when there is an increasing signal level, and causes the sigma-delta modulator to remain stable.
摘要翻译： Σ-Δ调制器，包括N阶低通滤波器，它由N个一阶积分部分（6.1,6.2,6.3，...，6.N）的串联组合构成，包括每个积分器（12.1 ，12.2,12.3，...，12.N）和限制器（14.1,14.2,14.3，...，14.N）。通过对应的加权放大器（16.1,16.2,16.3，...，16.N）对这些部分的各个输出信号进行加权，并在加法器级（18）中相加。选择这些部分的增益和限制器的限制值，使得当Σ-Δ调制器中的信号电平增加时，串联装置中的最后限制器（14.N）首先被激活，随后是最后一个限制器等。当存在增加的信号电平时，这会每次减少滤波器系统的次序，并且使Σ-Δ调制器保持稳定。

2. 发明授权

EP0208371B1 Digital-to-analog converter 失效转让
标题翻译：数字到模拟转换器
公开(公告)号：EP0208371B1
公开(公告)日：1990-06-13
申请号：EP86201135.0
申请日：1986-06-27
申请人： Philips Electronics N.V.
发明人： Dijkmans, Eise Carel
IPC分类号： H03M3/02
CPC分类号： H03M3/376 , H03M3/50

3. 发明授权

EP0196131B1 Amplifier arrangement 失效转让
公开(公告)号：EP0196131B1
公开(公告)日：1990-05-30
申请号：EP86200396.9
申请日：1986-03-12
申请人： Philips Electronics N.V.
发明人： Dijkmans, Eise Carel , Raets, Joseph Ghislain Gerard , Philips, Norbert Jeanne Louis
IPC分类号： H03F1/02 , H03F3/50
CPC分类号： H03F1/0244

4. 发明公开

EP0196131A1 Amplifier arrangement 失效转让
标题翻译：放大器排列
公开(公告)号：EP0196131A1
公开(公告)日：1986-10-01
申请号：EP86200396.9
申请日：1986-03-12
申请人： Philips Electronics N.V.
发明人： Dijkmans, Eise Carel , Raets, Joseph Ghislain Gerard , Philips, Norbert Jeanne Louis
IPC分类号： H03F1/02 , H03F3/50
CPC分类号： H03F1/0244
摘要： A high-efficiency amplifier of the class-G type comprises a first transistor (Ti), whose collector is connected to a first supply voltage (V 1 )via a first diode (D 1 ), and a second transistor (T 2 ), which is connected in series with said first transistor and which has its collector connected to a second supply voltage (V 2 ). The first transistor (T i ) is driven via a third transistor (T 3 ), which is arranged as an emitter follower by means of a first current source (5), the input voltage (V i ) being applied to this third transistor. For a low input voltage (V i ) the second transistor (T 2 ) is cut off and the first transistor (T 1 ) is connected to the first supply voltage (V 1 ) via the first diode (D 1 ). Above a specific inputvoltage (Vi) the second transistor (T 2 ) is driven into conduction by means of a driver circuit, so that the first transistor (T i ) is connected to the second supply voltage (V 2 ). This driver circuit comprises a first current path which is arranged between the second supply voltage (V 2 ) and the emitter of the third transistor (T 3 ) and which comprises the series arrangement of a second current source (7), the emitter-collector path of a fourth transistor (T 5 ) and a second diode (D 4 ), and a second current path which is arranged between the junction point (3) between the first transistor and the second transistor (T 1 , T 2 ) and the common point (11) and which comprises the series arrangement of a third diode (D 3 ), a fourth diode (D 4 ) and a third current source (8). The base of the fourth transistor (T 4 ) is connected to the junction point (9) between the third diode and the fourth diode (D 2 , D 3 ) and the collector of the fourth transistor (T 5 ) is connected to the third current source (8) by means of a fifth diode (0 5 ). By means of such a driver circuit it is possible to drive the outpur (2) to the value of the second supply voltage (V 2 ) minus substantially one base-emitter voltage.
摘要翻译： G类型的高效放大器包括其集电极通过第一二极管（D1）连接到第一电源电压（V1）的第一晶体管（T1）和连接到第二晶体管（T2）的第二晶体管（T2）与所述第一晶体管串联并且其集电极连接到第二电源电压（V2）。第一晶体管（Ti）经由第三晶体管（T3）被驱动，该第三晶体管（T3）借助于第一电流源（5）被布置为射极跟随器，输入电压（Vi）被施加到该第三晶体管。对于低输入电压（V 1），第二晶体管（T 2）截止并且第一晶体管（T 1）经由第一二极管（D 1）连接到第一电源电压（V 1）。在特定输入电压（Vi）以上，第二晶体管（T2）通过驱动器电路被驱动为导通，使得第一晶体管（Ti）连接到第二电源电压（V2）。该驱动器电路包括布置在第二电源电压（V2）和第三晶体管（T3）的发射极之间并且包括第二电流源（7）的串联布置的第一电流路径，发射极 - 集电极路径第四晶体管T5和第二二极管D4以及布置在第一晶体管和第二晶体管T1和T2之间的连接点3和公共点11之间的第二电流路径和其包括第三二极管（D3），第四二极管（D4）和第三电流源（8）的串联布置。第四晶体管（T4）的基极连接到第三二极管和第四二极管（D2，D3）之间的连接点（9），并且第四晶体管（T5）的集电极连接到第三电流源（8 ）借助于第五二极管（05）。借助于这样的驱动器电路，可以将输出端（2）驱动至第二电源电压（V2）的值减去基本上一个基极 - 发射极电压。

5. 发明授权

EP0065795B1 Digital-to-analog converter for bipolar signals 有权
标题翻译：用于双极信号的数字到模拟转换器
公开(公告)号：EP0065795B1
公开(公告)日：1984-07-25
申请号：EP82200520.3
申请日：1982-05-03
申请人： Philips Electronics N.V.
发明人： van de Plassche, Rudy Johan , Dijkmans, Eise Carel
IPC分类号： H03K13/05
CPC分类号： H03M1/0607

6. 发明公开

EP0096944A1 Schaltungsanordnung mit mehreren, durch aktive Schaltungen gebildeten Signalpfaden 失效
标题翻译：具有多个通过信号路径形成有源电路的电路布置。
公开(公告)号：EP0096944A1
公开(公告)日：1983-12-28
申请号：EP83200872.6
申请日：1983-06-15
申请人： Philips Patentverwaltung GmbH , Philips Electronics N.V.
发明人： Graffenberger, Wilhelm , Kilian, Ernst-August , Dijkmans, Eise Carel
IPC分类号： H03F3/72 , H03K17/16
CPC分类号： H03K17/6292 , H03F1/305 , H03F3/72 , H03K17/16 , H03K17/602
摘要： Die Erfindung betrifft eine Schaltungsanordnung mit verschiedenen Signalpfaden (31, 32; 41, 42; 51, 52) die durch schaltbare Stromquellen (3, 4, 5) aktivierbar sind. Als Stromquellen werden | 2 L-Gatter benutzt, deren Injektoranschlüsse in zwei Gruppen (A, B) zusammengefaßt sind. Beim Übergang von einem Signalpfad auf einen anderen, wird dem Injektoranschluß des mit dem einen Signalpfad verbundenen | 2 L-Gatters ein abnehmender und dem entsprechenden Anschluß des dem anderen Signalpfad zugeordneten 1 2 L-Gatters ein zunehmender Strom zugeführt.
摘要翻译：本发明涉及一种具有不同的信号路径的电路装置（31，32; 41，42; 51，52）通过开关的电流源（3，4，5）被激活。作为电流源I²L栅极中使用的，喷射器的连接被组合成两个组（A，B）。从一个信号路径过渡到另一个时，喷射器端口被提供给相关联的信号路径，所述一个I²L栅极，降低和相关联的信号路径的其他I²L栅极，一个增加的电流对应的端口。

7. 发明授权

EP0185411B1 Switching device for suppressing a signal 有权转让
标题翻译：用于抑制信号的切换装置
公开(公告)号：EP0185411B1
公开(公告)日：1990-03-14
申请号：EP85201915.7
申请日：1985-11-21
申请人： Philips Electronics N.V.
发明人： Dijkmans, Eise Carel
IPC分类号： H03F3/72 , H03G3/34
CPC分类号： H03F3/72 , H03G3/348

8. 发明公开

EP0342736A1 Phase-locked-loop cicuit and bit-detection arrangement comprising such a phase-locked-loop circuit 失效转让
标题翻译：锁相环电路和Bitdetektorschaltung与这样的锁相环电路。
公开(公告)号：EP0342736A1
公开(公告)日：1989-11-23
申请号：EP89201181.8
申请日：1989-05-10
申请人： Philips Electronics N.V.
发明人： Van Rens, Antonia Cornelia , Dijkmans, Eise Carel , Stikvoort, Edward Ferdinand
IPC分类号： H03L7/08
CPC分类号： H03L7/085 , G11B20/1403 , H03L7/0991 , H03L2207/50 , H04L7/0334
摘要： A digital phase-locked-loop circuit is revealed for deriving from a sequence of samples (J₁, ... J₂₀) of a band-limited data signal (Vt) the phase of the data signal at the sampling instants. The circuit comprises a discrete-time oscillator 10 for generating a sequence of phase values (F₁, ... F₂₀) which characterise a periodic signal (Vkl) which varies as a linear function of time between two constant limit values (E, -E). The frequency of the signal (Vk1) characterized by the phase value is proportional to a control value (I).
An interpolation circuit (2) derives from the sampes (J₁, ... J₂₀) the relative positions (tf/T) occupied by the detection-level crossings of the data signal (Vt) relative to the sampling instants. A phase detector (3) derives the difference (ΔF) between the actual phase of the data signal (Vt) and the phase as indicated by the phase values (F) from said relative positions (tf/T) and the phase values (F). By means of a digital sequential filter (9) the discrete-time oscillator (10) is controlled in such a way that said phase difference remains substantially zero. Moreover, a bit-detection arrangement comprising the phase-locked-loop circuit is revealed.
摘要翻译：一种数字锁相环电路被揭示用于从频带限制数据信号（VT）的数据信号的，在所述采样时刻的相位的采样的序列（J1 ... J20）导出。该电路包括一个离散时间振荡器10，用于产生相位值（F1 ... F20）表征的周期信号（VKL）而变化作为时间两个恒定限值（E，E之间的线性函数的一个序列）。由相位值表征了信号（VK1）的频率成比例的控制值（I）。内插电路（2）从sampes（J1 ... J20）由数据信号（Vt）的相对于采样时刻的所述检测电平交叉点所占据的相对位置（TF / T）派生的。相位检测器（3）导出数据信号（VT）和所指示的通过从所述相对位置（TF / T）的相位值（F）的相位的实际相位之间的差（DELTA F）和相位值（ F）。由数字滤波器顺序（9）的离散时间振荡器（10）的装置是控制在寻求一种方式，所述相位差保持基本上为零。更多，有一点检测装置，其包括相位锁定环电路被揭示。

9. 发明公开

EP0329231A1 Current source arrangement 失效
标题翻译：电流源安排
公开(公告)号：EP0329231A1
公开(公告)日：1989-08-23
申请号：EP89200305.4
申请日：1989-02-10
申请人： Philips Electronics N.V.
发明人： Schouwenaars, Hendrikus Johannes , Dijkmans, Eise Carel , Groeneveld, Dirk Wouter Johannes
IPC分类号： H01L27/02 , H03M1/76
CPC分类号： H03M1/0648 , H01L27/0229 , H01L27/1024 , H03M1/745
摘要： To improve the accuracy of a current source arrangement comprising a number of binary-weighted current sources, each of these current sources is constituted by a plurality of transistors which are arranged regularly in a matrix on the surface area of an integrated circuit.
摘要翻译：为了提高包括许多二进制加权电流源的电流源装置的精度，这些电流源中的每一个都由多个晶体管构成，这些晶体管在集成电路的表面区域上以规则排列的矩阵排列。

10. 发明公开

EP0199381A1 Amplifier arrangement 失效转让
标题翻译：放大器电路。
公开(公告)号：EP0199381A1
公开(公告)日：1986-10-29
申请号：EP86200398.5
申请日：1986-03-12
申请人： Philips Electronics N.V.
发明人： Dijkmans, Eise Carel , Raets, Joseph Ghislain Gerard , Philips, Norbert Jeanne Louis
IPC分类号： H03F1/02 , H03F3/50
CPC分类号： H03F1/0244 , H03F1/0233
摘要： A high-efficiency class-G type amplifier comprises a first transistor (T 1 ), whose collector is connected to a first supply voltage (V,) via a first diode (D 1 ) and a second transistor (T 2 ), which is connected in series with said first transistor and which has its collector connected to a second supply voltage (V 2 ). The series arrangement of a second (D 2 ), a third (D 3 ) and a fourth diode (D 4 ) is arranged between the bases of the first and the second transistor (T 1 , T 2 ), the fourth diode (D 4 ) being poled in a direction opposite to that of the second (D 2 ) and the third diode (D 3 ). By means of the series arrangement of a first resistor (R,) and the emitter-collector path of a first current-source transistor (T 4 ) the second supply voltage (V 2 ) is connected to the anode (4) of the fourth diode (D 4 ). The junction point (5) between the first resistor (R 1 ) and the current-source transistor (T 4 ) is connected to the output (2) of the arrangement by means of a capacitor (C 1 ). By means of such an arrangement the output (2) can be driven to a voltage substantially equal to the second voltage (V 2 ).

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