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1. 发明公开

EP1057117A2 VERFAHREN ZUM HIERARCHISCHEN CACHEN VON KONFIGURATIONSDATEN VON DATENFLUSSPROZESSOREN UND BAUSTEINEN MIT ZWEI- ODER MEHRDIMENSIONALER PROGRAMMIERBARER ZELLSTRUKTUR (FPGAs, DPGAs, o.dgl.) 有权
标题翻译：方法分层CACHEN组态数据的数据流处理器和功能块有两个或多维可编程单元结构（FPGA中，DPGAs，等等。）
公开(公告)号：EP1057117A2
公开(公告)日：2000-12-06
申请号：EP99913087.5
申请日：1999-02-25
申请人： Pact Informationstechnologie GmbH
发明人： VORBACH, Martin , MÜNCH, Robert
IPC分类号： G06F15/78 , G06F12/08
CPC分类号： G06F15/7867 , G06F12/0811 , G06F12/0813 , G06F12/084
摘要： Up until now, a central and global unit have been integrated into one module which processes all of the configuration requests. The invention provides for a plurality of active units which can take over this task. These units are arranged in a hierarchy. A request from the lowest level is only transferred to the next highest level if the request cannot be processed. The highest level is connected to an internal or external higher-order configuration memory which contains all the configuration data ever required for this programme run. The tree structure of the configuration units enables a kind of cacheing of the configuration data. The configurations are mainly accessed locally. In the worst case scenario, a configuration has to be loaded from the higher-order configuration memory in case the relative data are not available in any of the CTs (configuration tables) in the hierarchy.

2. 发明公开

EP1040420A1 VERFAHREN ZUR REPARATUR VON INTEGRIERTEN SCHALTKREISEN 有权
标题翻译：方法的修复集成电路
公开(公告)号：EP1040420A1
公开(公告)日：2000-10-04
申请号：EP98966545.0
申请日：1998-12-15
申请人： Pact Informationstechnologie GmbH
发明人： VORBACH, Martin , MÜNCH, Robert
IPC分类号： G06F11/267 , G01R31/3185 , G06F11/20
CPC分类号： G06F13/4068 , G01R31/318505 , G01R31/31908 , G06F11/006 , G06F11/2038 , G11C29/78
摘要： In addition to one or more subassemblies, an extra identical subassembly is provided. A multiplexer is connected to the inputs to the subassembly and connects the input bus of one subassembly to the following subassembly. The outputs of the subassembly are connected to a multiplexer which receives the output bus of each subassembly from the respective following subassembly. In the event of a defect in one of the subassemblies, the multiplexers are switched to replace the faulty subassembly with the following one, and so on unit the last subassembly is replaced by the extra subassembly.

3. 发明公开

EP0960374A2 INTERNES BUSSYSTEM FÜR DFPS, SOWIE BAUSTEINE MIT ZWEI- ODER MEHRDIMENSIONALEN PROGRAMMIERBAREN ZELLSTRUKTUREN, ZUR BEWÄLTIGUNG GROSSER DATENMENGEN MIT HOHEM VERNETZUNGSAUFWAND 失效
标题翻译：内部总线系统FOR DFPS以及具有两个或多维可编程单元结构块以满足成本高大量数据网络
公开(公告)号：EP0960374A2
公开(公告)日：1999-12-01
申请号：EP98909365.0
申请日：1998-02-11
申请人： Pact Informationstechnologie GmbH
发明人： VORBACH, Martin , MÜNCH, Robert
IPC分类号： G06F15 , G06F13 , H03K19
CPC分类号： H03K19/17736 , H03K19/17704 , H03K19/17796
摘要： The invention relates to a bus system for DFPs DE 16 88 A1 and to building blocks with two dimensional or multidimensional programmable cell structures (of type FPGA, DPGA or the like), characterized in that a) the bus system comprises a plurality of electrically independent bus segments disconnected by nodes, b) the nodes actively connect or disconnect bus segments, whereby b1) several bus segments are joined and connected by gates to a bus bar located inside the node or b2) connection occurs directly via circuitry elements, drivers and/or registers, c) each node has a routing table where information on the structure of the connection is stored, d) each node has a monitoring unit, which verifies independently if a connection can be established or not.

4. 发明授权

EP1057117B1 VERFAHREN ZUM HIERARCHISCHEN CACHEN VON KONFIGURATIONSDATEN VON DATENFLUSSPROZESSOREN UND BAUSTEINEN MIT ZWEI- ODER MEHRDIMENSIONALER PROGRAMMIERBARER ZELLSTRUKTUR (FPGAs, DPGAs, o.dgl.) 有权
标题翻译：方法分层CACHEN组态数据的数据流处理器和功能块有两个或多维可编程单元结构（FPGA中，DPGAs，等等。）
公开(公告)号：EP1057117B1
公开(公告)日：2002-05-15
申请号：EP99913087.5
申请日：1999-02-25
申请人： Pact Informationstechnologie GmbH
发明人： VORBACH, Martin , MÜNCH, Robert
IPC分类号： G06F15/78 , G06F12/08
CPC分类号： G06F15/7867 , G06F12/0811 , G06F12/0813 , G06F12/084
摘要： Up until now, a central and global unit have been integrated into one module which processes all of the configuration requests. The invention provides for a plurality of active units which can take over this task. These units are arranged in a hierarchy. A request from the lowest level is only transferred to the next highest level if the request cannot be processed. The highest level is connected to an internal or external higher-order configuration memory which contains all the configuration data ever required for this programme run. The tree structure of the configuration units enables a kind of cacheing of the configuration data. The configurations are mainly accessed locally. In the worst case scenario, a configuration has to be loaded from the higher-order configuration memory in case the relative data are not available in any of the CTs (configuration tables) in the hierarchy.

5. 发明授权

EP1057102B1 VERFAHREN ZUR DEADLOCKFREIEN KONFIGURATION VON DATENFLUSSPROZESSOREN UND BAUSTEINEN MIT ZWEI- ODER MEHRDIMENSIONALER PROGRAMMIERBARER ZELLSTRUKTUR (FPGAs, DPGAs, O. DGL.) 有权
标题翻译：方法DEADLOCKFREIEN配置数据流处理器和功能块有两个或多维可编程单元结构（FPGA中，DPGAs，等等。）
公开(公告)号：EP1057102B1
公开(公告)日：2002-05-15
申请号：EP99914430.6
申请日：1999-02-25
申请人： Pact Informationstechnologie GmbH
发明人： VORBACH, Martin , MÜNCH, Robert
IPC分类号： G06F9/00
CPC分类号： G06F15/7867 , G06F12/0811 , G06F12/0813 , G06F12/084
摘要： Up until now, a central and global unit have been integrated into one module which processes all of the configuration requests. The invention provides for a plurality of active units which can take over this task. These units are arranged in a hierarchy. A request from the lowest level is only transferred to the next highest level if the request cannot be processed. The highest level is connected to an internal or external higher-order configuration memory which contains all the configuration data ever required for this programme run. Deadlocks are avoided through the introduction of a fixed chronological order of the configurations to be loaded and through the organisation of the configurations into a list. The CEL (cell) status information is secured before loading and therefore remains unchanged throughout the processing of the entire list of configurations.

6. 发明公开

EP0947049A1 UMKONFIGURIERUNGS-VERFAHREN FÜR PROGRAMMIERBARE BAUSTEINE ZUR LAUFZEIT 失效
标题翻译：重构方法可编程块到期
公开(公告)号：EP0947049A1
公开(公告)日：1999-10-06
申请号：EP97954333.0
申请日：1997-12-22
申请人： Pact Informationstechnologie GmbH
发明人： VORBACH, Martin , MÜNCH, Robert
IPC分类号： G06F9 , G06F15 , H03K19
CPC分类号： G06F15/7867 , G06F9/24
摘要： The invention relates to a method for reconfiguration during the running time of FPGA, in which there is a loading logic or several loading logics which react to signals of any kind and recognize and can process special loading logic commands within a configuration programme consisting of data and commands, and, on the basis of the source of an event, can compute an entry in a branch table. For this, there are one or more branch tables for locating the address of the configuration data to be loaded after computing. One or more configuration memory areas exist, in which one or more configuration programmes are loaded; and there are one or more FIFO memory areas into which configuration data is copied which could not be sent to the element or elements to be configured. When an event occurs, an address is computed in a branch table, based on the source of the event. FIFO memory area is provided and run through before each reloading, and, if the cell can not be reloaded, the configuration data is copied into it nearer the beginning; if the cell can be reloaded, the configuration data is transferred to the cell. The computed branch table entry is read-out, and the configuration data which is stored at the read-out address is loaded into the cell, or, if the cell cannot be reprogrammed, it is copied into the FIFO memory area.

7. 发明授权

EP0951682B1 IO- UND SPEICHERBUSSYSTEM FÜR DFPs SOWIE BAUSTEINE MIT ZWEI- ODER MEHRDIMENSIONALEN PROGRAMMIERBAREN ZELLSTRUKTUREN 失效
标题翻译： IO和存储器总线SYSTEM FOR指定联络点以及具有两个或多维可编程单元结构积木
公开(公告)号：EP0951682B1
公开(公告)日：2003-06-25
申请号：EP97953672.9
申请日：1997-12-21
申请人： Pact Informationstechnologie GmbH
发明人： VORBACH, Martin , MÜNCH, Robert
IPC分类号： G06F15/78
CPC分类号： G06F15/7867 , G11C7/10
摘要： The invention relates to a bus system produced by concentrating individual conductors or buses within a unit of the type DFP, FPGA, DPGA, as well as all units with two- or multi-dimensionally programmable cell structure, and via which the units can be assembled to form several and/or can be connected to a memory and/or a periphery.
摘要翻译：该系统具有若干捆绑个别线或总线或局部总线与二维或多维可编程单元结构的组件内，使得能够与其他组合和/或连接到存储器和/或外围设备的组件。一个或多个接口被用于将线结合并设置总线系统，该接口由一个或多个状态机控制。

8. 发明公开

EP1057102A2 VERFAHREN ZUR DEADLOCKFREIEN KONFIGURATION VON DATENFLUSSPROZESSOREN UND BAUSTEINEN MIT ZWEI- ODER MEHRDIMENSIONALER PROGRAMMIERBARER ZELLSTRUKTUR (FPGAs, DPGAs, O. DGL.) 有权
标题翻译：方法DEADLOCKFREIEN配置数据流处理器和功能块有两个或多维可编程单元结构（FPGA中，DPGAs，等等。）
公开(公告)号：EP1057102A2
公开(公告)日：2000-12-06
申请号：EP99914430.6
申请日：1999-02-25
申请人： Pact Informationstechnologie GmbH
发明人： VORBACH, Martin , MÜNCH, Robert
IPC分类号： G06F9/00
CPC分类号： G06F15/7867 , G06F12/0811 , G06F12/0813 , G06F12/084
摘要： Up until now, a central and global unit have been integrated into one module which processes all of the configuration requests. The invention provides for a plurality of active units which can take over this task. These units are arranged in a hierarchy. A request from the lowest level is only transferred to the next highest level if the request cannot be processed. The highest level is connected to an internal or external higher-order configuration memory which contains all the configuration data ever required for this programme run. Deadlocks are avoided through the introduction of a fixed chronological order of the configurations to be loaded and through the organisation of the configurations into a list. The CEL (cell) status information is secured before loading and therefore remains unchanged throughout the processing of the entire list of configurations.

9. 发明公开

EP0951682A1 IO- UND SPEICHERBUSSYSTEM FÜR DFPs SOWIE BAUSTEINE MIT ZWEI- ODER MEHRDIMENSIONALEN PROGRAMMIERBAREN ZELLSTRUKTUREN 失效
标题翻译： IO和存储器总线SYSTEM FOR指定联络点以及具有两个或多维可编程单元结构积木
公开(公告)号：EP0951682A1
公开(公告)日：1999-10-27
申请号：EP97953672.0
申请日：1997-12-21
申请人： Pact Informationstechnologie GmbH
发明人： VORBACH, Martin , MÜNCH, Robert
IPC分类号： G06F13 , G06F15 , G11C7
CPC分类号： G06F15/7867 , G11C7/10
摘要： The invention relates to a bus system produced by concentrating individual conductors or buses within a unit of the type DFP, FPGA, DPGA, as well as all units with two- or multi-dimensionally programmable cell structure, and via which the units can be assembled to form several and/or can be connected to a memory and/or a periphery.

10. 发明公开

EP0948842A1 VERFAHREN ZUM SELBSTÄNDIGEN DYNAMISCHEN UMLADEN VON DATENFLUSSPROZESSOREN (DFPs) SOWIE BAUSTEINEN MIT ZWEI- ODER MEHRDIMENSIONALEN PROGRAMMIERBAREN ZELLSTRUKTUREN (FPGAs, DPGAs, o.dgl.) 失效
标题翻译：方法动态自RELOAD数据流处理器（DFP）块和具有两个或多维可编程单元结构（FPGA中，DPGAs，等等。）
公开(公告)号：EP0948842A1
公开(公告)日：1999-10-13
申请号：EP97954332.0
申请日：1997-12-22
申请人： Pact Informationstechnologie GmbH
发明人： VORBACH, Martin , MÜNCH, Robert
IPC分类号： G06F9 , G06F15
CPC分类号： G06F15/7867 , G06F9/30
摘要： The invention relates to a method for dynamic reconfiguration of FPGA, in which one or more switching tables consisting of one or more controls and one or more configuration storages are integrated in the module or connected thereto. Configuration words of a switching table are transferred to a configurable element or to multiple configurable elements of the module which then set a valid configuration. The load logic or the configurable elements of the module or modules can write data in the configuration storage or storages of the switching table or tables. The control of the switching table or tables can recognize individual inputs as instructions and execute them. The control can also recognize and distinguish different events and execute a relevant defined action. Upon reacting to the occurrence of an event or a combination of events, the control moves the position pointer or pointers. Whenever configuration data and not control instructions are concerned, the control sends said configuration data to the configurable element or elements declared in the configuration data.

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