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1. 发明公开

EP1915791A2 LASER ABLATION METHOD FOR FABRICATING HIGH PERFORMANCE ORGANIC DEVICES 审中-公开
标题翻译：激光消融有机高性能设备生产
公开(公告)号：EP1915791A2
公开(公告)日：2008-04-30
申请号：EP06801473.7
申请日：2006-08-14
申请人： Organicid, Inc.
发明人： DIMMLER, Klaus
IPC分类号： H01L51/40
CPC分类号： H01L51/102 , B82Y30/00 , H01L27/283 , H01L51/0023 , H01L51/0541 , H01L51/0545
摘要： A laser ablation method is utilized to define the channel length of an organic transistor. A substrate is coated with a deposition of a metal or conductive polymer deposition, applied in a thin layer in order to enhance the resolution that can be attained by laser ablation. The laser ablation method can be used in a roll-to-roll process, and achieves speeds, volumes, prices and resolutions that are adequate to produce printed electronic technologies.

2. 发明公开

EP1915790A2 METHOD OF FABRICATING ORGANIC FETS 审中-公开
标题翻译：用于生产机场效电晶体
公开(公告)号：EP1915790A2
公开(公告)日：2008-04-30
申请号：EP06801475.2
申请日：2006-08-14
申请人： Organicid, Inc.
发明人： DIMMLER, Klaus , ROTZOLL, Robert R.
IPC分类号： H01L51/00 , H01L51/40
CPC分类号： H01L51/052 , H01L27/283 , H01L51/0004 , H01L51/0541 , H01L51/0545
摘要： At least two thicknesses of dielectric are formed in the fabrication of organic field effect transistors. One thickness is formed in the active regions of the transistor for adjusting the desired threshold of the device. A second thickness is deposited in the field regions of the transistor to electrically isolate the transistors, and reduces leakage current and capacitance. A third dielectric thickness that is thicker than the first thickness but thinner than the second thickness can be used to define transistors having a second threshold voltage. The multiple dielectric thicknesses can be produced by multiple cell sizes of a gravure roll when using gravure printing, multiple cell sizes in an anolox roll in flexography printing, multiple nozzle size and chamber pressure in inkjet printing, or by printing successive layers of a single thickness of dielectric. The method can be employed in top gate, bottom gate top contact, and in bottom gate bottom contact organic transistor structures.

3. 发明公开

EP1706943A2 NON-QUASISTATIC PHASE LOCK LOOP FREQUENCY DIVIDER CIRCUIT 审中-公开
标题翻译：非准静态锁相环分频电路
公开(公告)号：EP1706943A2
公开(公告)日：2006-10-04
申请号：EP05705567.5
申请日：2005-01-11
申请人： Organicid, Inc.
发明人： ROTZOLL, Robert, R. , DIMMLER, Klaus
IPC分类号： H03L7/06
CPC分类号： H03L7/091 , H03K3/0315 , H03L7/0995
摘要： A non-quasistatic MOS frequency divider circuit uses a phase lock loop configuration including an antenna coil (802) to induce a differential input signal, an antenna resonating capacitor (804), a rectifier (806), a voltage controlled ring oscillator (808), a phase detector and a loop filter (824). All transistors used are organic MOS devices of PMOS, NMOS or both PMOS and NMOS varieties. The voltage-controlled oscillator includes a multiple delay stage ring oscillator. The phase detector includes transistors connected as sampling switches to sample the individual oscillator stage voltages into the loop filter. The sampling transistors have gates connected to the coil. The loop filter provides a substantially direct current to a loop amplifier and then to the voltage controlled oscillator delay control input. This configuration results in the voltage controlled oscillator frequency being synchronous to- and at a sub-multiple of the antenna signal frequency. The sampling transistor gates are all connected to the coil and thereby become part of the capacitance of the radio frequency parallel resonant network. The transistor gates are then efficiently switched at the rate of the radio frequency signal with no delay relative to the coil voltage. Operation of the phase detector organic transistors is based on non-quasistatic behaviour of the transistor. Non-quasistatic operation results in phase detection at a frequency much higher than the quasistatic limit of transistor unity gain bandwidth.

4. 发明公开

EP1719249A2 NON-QUASISTATIC RECTIFIER CIRCUIT 审中-公开
标题翻译： NOT准静态整流电路
公开(公告)号：EP1719249A2
公开(公告)日：2006-11-08
申请号：EP05705041.1
申请日：2005-01-05
申请人： Organicid, Inc.
发明人： ROTZOLL, Robert, R. , DIMMLER, Klaus
IPC分类号： H03K17/56
CPC分类号： H02M7/219 , H01L27/283 , H02M2007/2195 , Y02B70/1408 , Y02B70/1441
摘要： A non-quasistsic MOS rectifier circuit (530) uses a bridge-rectifier configuration using four organic PMOS transistors (Ml, M2, M3 and M4), an antenna coil (532) to induce a differential input signal, and an output capacitor (534) for filtering the rectified output signal. The VSS or ground-connected transistors are diode-connected with the gate connection on the coil side of the transistor channel. The VDD-connected transistors have gates connected to the opposing VDD-connected transistor source that is connected to the coil (532). This configuration results in full-wave rectification. The gates are all connected to the coil and thereby become part of of the capacitance of the radio frequency parallel resonant network. The transistor gates are then switched at the rate of the radio frequency signal with no delay relative to the coil voltage, Operation of the organic transistors is based on non-quasistatic behavior of the transistor. Non-quasistatic operation results in rectification at a frequenct much higher than the quasistatic limit of transistor unity gain bandwidth.

5. 发明公开

EP2011173A1 STRUCTURE AND FABRICATION OF SELF-ALIGNED HIGH-PERFORMANCE ORGANIC FETS 审中-公开
标题翻译：结构和制造自对准HIGH强大的有机FET的
公开(公告)号：EP2011173A1
公开(公告)日：2009-01-07
申请号：EP06846320.7
申请日：2006-11-16
申请人： Organicid, Inc.
发明人： DIMMLER, Klaus , ROTZOLL, Robert, R.
IPC分类号： H01L51/00
CPC分类号： H01L51/0022 , H01L27/283 , H01L51/0023 , H01L51/0036 , H01L51/0037 , H01L51/0042 , H01L51/0055 , H01L51/0059 , H01L51/052 , H01L51/057 , H01L51/102
摘要： A low channel length organic field-effect transistor can be produced in high volume and at low cost. The transistor structure includes successively deposited patterned layers of a first conductor layer acting as a source terminal, a first dielectric layer, a second conductor layer acting as a drain terminal, a semiconductor layer, a second dielectric layer, and a third conductor layer acting as the gate terminal. In this structure, the transistor is formed on the edge of the first dielectric between the first conductor layer and the second conductor layer. The second conductor layer is deposited on the raised surfaces formed by the dielectric such that conductive ink does not flow into the trough between the dielectric raised surfaces. This is accomplished by coating a flat or rotary print plate with the conductive ink, and applying the appropriate pressure to deposit the materials only on the raised surfaces of the dielectric. The second metal is automatically aligned to the layer beneath it. Due to this self-alignment and the short channel formed by the thickness of the dielectric material, a high-performance FET is produced without the requirement of high-resolution lithography equipment.

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