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1. 发明公开

EP1237282A1 Circuit for the detection of clock signal period abnormalities 有权
标题翻译：在einem Taktsignal的Schaltung zur Detektion vonStörungender Periodendauer
公开(公告)号：EP1237282A1
公开(公告)日：2002-09-04
申请号：EP02250671.1
申请日：2002-01-31
申请人： NEC CORPORATION
发明人： Senba, Hisanori, c/o NEC Micro Systems, Ltd.
IPC分类号： H03K21/40
CPC分类号： G01R31/31727 , H03K5/159 , H03K5/19
摘要： The invention provides for a clock monitoring circuit comprising a first flip-flop circuit for latching and outputting an input signal when a given transition of a clock signal occurs between its two logic levels, a second flip-flop circuit for latching and outputting the output signal of the first flip-flop circuit when a given transition of the clock signal occurs between its two logic levels, delay means for delaying the output signal of the second flip-flop circuit by a time interval that is shorter than a predetermined period of the clock signal and for outputting the resultant signal as an input signal to the first flip-flop circuit, and a gate circuit for receiving the output signal of the first flip-flop circuit and the output signal of the second flip-flop circuit, and for outputting a signal of a first logic level when the period of the clock signal is equal to, or greater than, the predetermined time interval and for outputting a signal of a second logic level when the period of the clock signal is shorter than the predetermined time interval.
摘要翻译：本发明提供了一种时钟监视电路，其包括第一触发器电路，用于当在其两个逻辑电平之间发生时钟信号的给定转换时锁存和输出输入信号;第二触发器电路，用于锁存和输出输出信号当在其两个逻辑电平之间发生时钟信号的给定转变时，第一触发器电路的延迟装置，用于将第二触发器电路的输出信号延迟比时钟的预定时间段的时间间隔信号并将所得到的信号作为输入信号输出到第一触发器电路;以及门电路，用于接收第一触发器电路的输出信号和第二触发器电路的输出信号，并用于输出当时钟信号的周期等于或大于预定时间间隔时，当第一逻辑电平的信号为第一逻辑电平时，输出第二逻辑电平的信号 d的时钟信号比预定的时间间隔短。

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