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1. 发明公开

EP1552529A2 METHOD AND APPARATUS FOR ERASING FLASH MEMORY 有权
标题翻译：方法和装置删除Flash存储器
公开(公告)号：EP1552529A2
公开(公告)日：2005-07-13
申请号：EP03756241.0
申请日：2003-05-29
申请人： Micron Technology, Inc.
发明人： MIHNEA, Andrei , CHEN, Chun
IPC分类号： G11C16/14
CPC分类号： G11C16/16 , G11C16/08 , G11C16/14 , H01L27/115
摘要： Method and apparatus for the erase of non-volatile memory in which holes trapped in the tunnel oxide are reduced. To avoid stress induced leakage current (SILC), which occurs when holes become trapped in the tunnel oxide of a flash memory, the following erase method is proposed. The erase is divided into a source erase (5 volt at source, -10 volt at the gate) followed by a channel erase (0 volt at source and -12 to -15 volt at the gate). The increased negative voltage (-12 to -15) can either be statically supplied by a voltage source or be dynamically generated by a “negative gate bootstrap” or capacitive voltage boosting. For boosting, the transition from source erase to channel erase (switching source rapidly in a fraction of a millisecond from 5 volt to 0 volt) capacitively couples the gate to approximately -15 volt. Boosting is improved, when the parasitic capacitance of the word line drivers is low compared to the capacitance between the source and the control gate of the memory transistor; and is additionally improved, when the drain leakage of the word line drivers is low (GIDL: gate induced drain leakage). Advantageously the word line drivers are provided with LDD (lightly doped drain) and a low k dielectric gate spacer.

2. 发明公开

EP1894244A2 NON-VOLATILE MEMORY CELLS WITHOUT DIFFUSION JUNCTIONS 审中-公开
标题翻译：非易失性存储单元无扩散链接
公开(公告)号：EP1894244A2
公开(公告)日：2008-03-05
申请号：EP06771809.8
申请日：2006-06-02
申请人： Micron Technology, Inc.
发明人： MIHNEA, Andrei , MORADI, Behnam , ARITOME, Seiichi , LI, Di , RUDECK, Paul
IPC分类号： H01L27/115 , H01L21/8247 , G11C16/04
CPC分类号： H01L27/115 , G11C16/0483 , H01L27/11521 , H01L27/11524 , H01L27/11568
摘要： A plurality of memory cell stacks (209-212) are formed over a substrate. The substrate does not have diffusion regions between each memory cell stack to link the memory cells. The cells are formed close enough such that the memory cells are linked serially by the electric fields (250-256) generated by each floating gate (222) in the channel regions. In one embodiment, an n- layer (230) is implanted at the top of the substrate to increase conductivity between cells. The select transistors can be linked to the serial string by diffusion regions or by interaction of the electric fields between the select transistor channel and the memory cell channel.

3. 发明公开

EP1535286A1 CONTACTLESS UNIFORM-TUNNELING SEPARATE P-WELL (CUSP) NON-VOLATILE MEMORY ARRAY ARCHITECTURE, FABRICATION AND OPERATION 有权
标题翻译：与非接触式SEPARATE P阱具有均匀隧道（CUSP），生产和操作阵列架构的非易失性存储器
公开(公告)号：EP1535286A1
公开(公告)日：2005-06-01
申请号：EP03791971.9
申请日：2003-08-29
申请人： Micron Technology, Inc.
发明人： CHEN, Chun , MIHNEA, Andrei , PRALL, Kirk, D.
IPC分类号： G11C16/04
CPC分类号： H01L27/11519 , H01L27/115 , H01L27/11521
摘要： Floating-gate field-effect transistors or memory cells formed in isolated wells are useful in the fabrication of non-volatile memory arrays and devices. A column of such floating-gate memory cells are associated with a well containing the source/drain regions for each memory cell in the column. These wells are isolated from source/drain regions of other columns of the array. Fowler-Nordheim tunneling can be used to program and erase such floating-gate memory cells either on an individual basis or on a bulk or block basis.

4. 发明授权

EP1535286B1 CONTACTLESS UNIFORM-TUNNELING SEPARATE P-WELL (CUSP) NON-VOLATILE MEMORY ARRAY ARCHITECTURE, FABRICATION AND OPERATION 有权
标题翻译：与非接触式SEPARATE P阱具有均匀隧道（CUSP），生产和操作阵列架构的非易失性存储器
公开(公告)号：EP1535286B1
公开(公告)日：2007-09-19
申请号：EP03791971.9
申请日：2003-08-29
申请人： MICRON TECHNOLOGY, INC.
发明人： CHEN, Chun , MIHNEA, Andrei , PRALL, Kirk, D.
IPC分类号： G11C16/04
CPC分类号： H01L27/11519 , H01L27/115 , H01L27/11521
摘要： Floating-gate field-effect transistors or memory cells formed in isolated wells are useful in the fabrication of non-volatile memory arrays and devices. A column of such floating-gate memory cells are associated with a well containing the source/drain regions for each memory cell in the column. These wells are isolated from source/drain regions of other columns of the array. Fowler-Nordheim tunneling can be used to program and erase such floating-gate memory cells either on an individual basis or on a bulk or block basis.

5. 发明授权

EP1552529B1 METHOD AND APPARATUS FOR ERASING FLASH MEMORY 有权
标题翻译：方法和装置删除Flash存储器
公开(公告)号：EP1552529B1
公开(公告)日：2010-11-03
申请号：EP03756241.0
申请日：2003-05-29
申请人： Micron Technology, Inc.
发明人： MIHNEA, Andrei , CHEN, Chun
IPC分类号： G11C16/14
CPC分类号： G11C16/16 , G11C16/08 , G11C16/14 , H01L27/115
摘要： Method and apparatus for the erase of non-volatile memory in which holes trapped in the tunnel oxide are reduced. To avoid stress induced leakage current (SILC), which occurs when holes become trapped in the tunnel oxide of a flash memory, the following erase method is proposed. The erase is divided into a source erase (5 volt at source, -10 volt at the gate) followed by a channel erase (0 volt at source and -12 to -15 volt at the gate). The increased negative voltage (-12 to -15) can either be statically supplied by a voltage source or be dynamically generated by a “negative gate bootstrap” or capacitive voltage boosting. For boosting, the transition from source erase to channel erase (switching source rapidly in a fraction of a millisecond from 5 volt to 0 volt) capacitively couples the gate to approximately -15 volt. Boosting is improved, when the parasitic capacitance of the word line drivers is low compared to the capacitance between the source and the control gate of the memory transistor; and is additionally improved, when the drain leakage of the word line drivers is low (GIDL: gate induced drain leakage). Advantageously the word line drivers are provided with LDD (lightly doped drain) and a low k dielectric gate spacer.

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