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1. 发明授权

EP1535286B1 CONTACTLESS UNIFORM-TUNNELING SEPARATE P-WELL (CUSP) NON-VOLATILE MEMORY ARRAY ARCHITECTURE, FABRICATION AND OPERATION 有权
标题翻译：与非接触式SEPARATE P阱具有均匀隧道（CUSP），生产和操作阵列架构的非易失性存储器
公开(公告)号：EP1535286B1
公开(公告)日：2007-09-19
申请号：EP03791971.9
申请日：2003-08-29
申请人： MICRON TECHNOLOGY, INC.
发明人： CHEN, Chun , MIHNEA, Andrei , PRALL, Kirk, D.
IPC分类号： G11C16/04
CPC分类号： H01L27/11519 , H01L27/115 , H01L27/11521
摘要： Floating-gate field-effect transistors or memory cells formed in isolated wells are useful in the fabrication of non-volatile memory arrays and devices. A column of such floating-gate memory cells are associated with a well containing the source/drain regions for each memory cell in the column. These wells are isolated from source/drain regions of other columns of the array. Fowler-Nordheim tunneling can be used to program and erase such floating-gate memory cells either on an individual basis or on a bulk or block basis.

2. 发明授权

EP2923378B1 TRANSISTORS, MEMORY CELLS AND SEMICONDUCTOR CONSTRUCTIONS 有权
公开(公告)号：EP2923378B1
公开(公告)日：2020-01-22
申请号：EP13856981.9
申请日：2013-10-15
申请人： Micron Technology, Inc.
发明人： RAMASWAMY, Nirmal , PRALL, Kirk, D. , KINNEY, Wayne
IPC分类号： H01L27/108 , H01L29/423 , H01L29/51 , H01L29/66 , H01L21/28 , H01L29/78 , H01L27/11585 , H01L29/08 , G11C14/00 , H01L29/40 , H01L29/10

3. 发明公开

EP2923378A1 TRANSISTORS, MEMORY CELLS AND SEMICONDUCTOR CONSTRUCTIONS 有权
标题翻译：晶体管，存储单元与半导体结构
公开(公告)号：EP2923378A1
公开(公告)日：2015-09-30
申请号：EP13856981.9
申请日：2013-10-15
申请人： Micron Technology, Inc.
发明人： RAMASWAMY, Nirmal , PRALL, Kirk, D. , KINNEY, Wayne
IPC分类号： H01L27/108
摘要： Some embodiments include a semiconductor construction having a gate extending into a semiconductor base. Conductively-doped source and drain regions are within the base adjacent the gate. A gate dielectric has a first segment between the source region and the gate, a second segment between the drain region and the gate, and a third segment between the first and second segments. At least a portion of the gate dielectric comprises ferroelectric material. In some embodiments the ferroelectric material is within each of the first, second and third segments. In some embodiments, the ferroelectric material is within the first segment or the third segment. In some embodiments, a transistor has a gate, a source region and a drain region; and has a channel region between the source and drain regions. The transistor has a gate dielectric which contains ferroelectric material between the source region and the gate.

4. 发明公开

EP1929509A2 PITCH MULTIPLICATION SPACERS AND METHODS OF FORMING THE SAME 审中-公开
标题翻译：距离乘以距离元件和生产工艺研究
公开(公告)号：EP1929509A2
公开(公告)日：2008-06-11
申请号：EP06790064.7
申请日：2006-08-28
申请人： Micron Technology, Inc.
发明人： SANDHU, Gurtej, S. , PRALL, Kirk, D.
IPC分类号： H01L21/033 , H01L21/308 , H01L21/321 , H01L21/027
CPC分类号： H01L21/67063 , H01L21/0337 , H01L21/0338 , H01L21/3086 , H01L21/3088 , H01L21/32053 , H01L21/32134
摘要： Spacers (175) in a pitch multiplication process are formed without performing a spacer etch. Rather, mandrels (145) are formed over a substrate (110) and then the sides of the mandrels (145) are reacted, e.g., in an oxidization, nitridation, or silicidation step, to form a material that can be selectively removed relative to the unreacted portions of the mandrel (145). The unreacted portions are selectively removed to leave a pattern of free- standing spacers (175). The free-standing spacers (175) can serve as a mask for subsequent processing steps, such as etching the substrate (110).

6. 发明公开

EP1535286A1 CONTACTLESS UNIFORM-TUNNELING SEPARATE P-WELL (CUSP) NON-VOLATILE MEMORY ARRAY ARCHITECTURE, FABRICATION AND OPERATION 有权
标题翻译：与非接触式SEPARATE P阱具有均匀隧道（CUSP），生产和操作阵列架构的非易失性存储器
公开(公告)号：EP1535286A1
公开(公告)日：2005-06-01
申请号：EP03791971.9
申请日：2003-08-29
申请人： Micron Technology, Inc.
发明人： CHEN, Chun , MIHNEA, Andrei , PRALL, Kirk, D.
IPC分类号： G11C16/04
CPC分类号： H01L27/11519 , H01L27/115 , H01L27/11521
摘要： Floating-gate field-effect transistors or memory cells formed in isolated wells are useful in the fabrication of non-volatile memory arrays and devices. A column of such floating-gate memory cells are associated with a well containing the source/drain regions for each memory cell in the column. These wells are isolated from source/drain regions of other columns of the array. Fowler-Nordheim tunneling can be used to program and erase such floating-gate memory cells either on an individual basis or on a bulk or block basis.

7. 发明公开

EP0907967A2 SOI-TRANSISTOR CIRCUITRY EMPLOYING SOI-TRANSISTORS AND METHOD OF MANUFACTURE THEREOF 失效
标题翻译： SOI三极管，开关SOI晶体管的应用及其生产工艺
公开(公告)号：EP0907967A2
公开(公告)日：1999-04-14
申请号：EP97931250.0
申请日：1997-06-18
申请人： MICRON TECHNOLOGY, INC.
发明人： PRALL, Kirk, D.
IPC分类号： H01L21 , H01L27 , H01L29
CPC分类号： H01L27/1203 , H01L21/84 , H01L29/78642 , Y10S257/905
摘要： The invention includes several aspects related to semiconductor-on-insulator transistors, to memory and other DRAM circuitry and arrays, to transistor gate arrays, and to methods of fabricating such constructions. In one aspect, a semiconductor-on-insulator transistor includes: a) an insulator layer; b) a layer of semiconductor material over the insulator layer; c) a transistor gate provided within the semiconductor material layer; and d) an outer elevation source/drain diffusion region and an inner elevation diffusion region provided within the semiconductor material layer in operable proximity to the transistor gate. In another aspect, DRAM circuitry includes a plurality of memory cells not requiring sequential access, at least a portion of the plurality having more than two memory cells for a single bit line contact. In still another aspect, a DRAM array of memory cells comprises a plurality of wordlines, source regions, drain regions, bit lines in electrical connection with the drain regions, and storage capacitors in electrical connection with the source regions; at least two drain regions of different memory cells being interconnected with one another beneath one of the wordlines. In yet another aspect, a DRAM array has more than two memory cells for a single bit line contact, and a plurality of individual memory cells occupy a surface area of less than or equal to 2f X (2f + f/N), where 'f' is the minimum photolithographic feature size with which the array was fabricated, and 'N' is the number of memory cells per single bit line contact within the portion.

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