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1. 发明授权

EP2838234B1 SIGNAL TRANSMISSION SYSTEM 有权
公开(公告)号：EP2838234B1
公开(公告)日：2019-08-14
申请号：EP13776218.3
申请日：2013-03-19
申请人： Mitsubishi Electric Corporation
发明人： TAJIMA, Kenichi , KAWAKAMI, Kenji , HIRAI, Akihito , HIRAMINE, Masanobu
IPC分类号： H04L25/49 , H03M5/12

2. 发明公开

EP2838234A1 SIGNAL TRANSMISSION DEVICE 审中-公开
标题翻译：信号传输装置
公开(公告)号：EP2838234A1
公开(公告)日：2015-02-18
申请号：EP13776218.3
申请日：2013-03-19
申请人： Mitsubishi Electric Corporation
发明人： TAJIMA, Kenichi , KAWAKAMI, Kenji , HIRAI, Akihito , HIRAMINE, Masanobu
IPC分类号： H04L25/49 , H03M5/12
CPC分类号： H04L25/4902 , H03M5/12
摘要： A signal transmission system has a modulation signal converter 1 that generates a modulation signal using a Manchester code with a duty ratio of 50% in accordance with transmission data; a clock generator 6 that generates a clock with the amount of delay with respect to the rising or falling edge of the modulation signal; and a data detector 5 that generates received data by sampling the modulation signal in synchronization with the clock. Since the modulation signal converter 1 generates the modulation signal by combining the Manchester code with the duty ratio of 50%, its duty ratio is always 50% independently of the transmission data, thereby preventing the DC offset of the modulation signal on the receiving side. Accordingly, it offers an advantage of achieving good communication quality with a simple circuit configuration without producing the DC offset in the modulation signal on the receiving side.
摘要翻译：信号传输系统具有调制信号转换器1，其根据传输数据使用占空比为50％的曼彻斯特码生成调制信号; 时钟发生器6，其产生相对于调制信号的上升沿或下降沿具有延迟量的时钟; 以及数据检测器5，其通过与时钟同步地对调制信号进行采样来生成接收数据。由于调制信号转换器1通过组合占空比为50％的曼彻斯特码来产生调制信号，所以其占空比总是与发送数据无关地为50％，由此防止接收侧的调制信号的DC偏移。相应地，它具有以简单的电路配置实现良好的通信质量而不在接收侧的调制信号中产生DC偏移的优点。

3. 发明公开

EP3896465A1 FREQUENCY DETECTION CIRCUIT 有权
公开(公告)号：EP3896465A1
公开(公告)日：2021-10-20
申请号：EP19911540.3
申请日：2019-01-22
申请人： MITSUBISHI ELECTRIC CORPORATION
发明人： WADA, Osamu , TAJIMA, Kenichi
IPC分类号： G01R23/02 , G01R13/34 , G01R23/16
摘要： Conventional frequency detection circuits have a disadvantage that the circuit scale increases as the frequency of a reception signal to be detected increases.
A frequency detection circuit of the present invention includes: a first signal source for outputting a first clock signal; a second signal source for outputting a second clock signal having the same frequency as but a different phase from those of the first clock signal; a first sample hold circuit for undersampling a reception signal using the first clock signal; a second sample hold circuit for undersampling the reception signal using the second clock signal; and a frequency calculating circuit for calculating the frequency of the reception signal using a phase difference between output signals of the first sample hold circuit and the second sample hold circuit.

4. 发明授权

EP3410602B1 PULSE SHIFT CIRCUIT AND FREQUENCY SYNTHESIZER 有权
公开(公告)号：EP3410602B1
公开(公告)日：2019-12-18
申请号：EP17762875.7
申请日：2017-02-20
申请人： Mitsubishi Electric Corporation
发明人： NAKAMIZO, Hideyuki , HIEDA, Morishige , MIZUTANI, Hiroyuki , TAJIMA, Kenichi
IPC分类号： H03L7/197 , H03L7/23 , H03M3/02

5. 发明公开

EP3410532A1 IN-PHASE DISTRIBUTION CIRCUIT AND ARRAY ANTENNA DEVICE 有权
公开(公告)号：EP3410532A1
公开(公告)日：2018-12-05
申请号：EP16889231.3
申请日：2016-02-02
申请人： Mitsubishi Electric Corporation
发明人： MIZUTANI, Hiroyuki , TAJIMA, Kenichi , HIEDA, Morishige
IPC分类号： H01P5/12 , H01Q3/30
CPC分类号： H01P1/18 , H01P1/213 , H01P1/24 , H01P1/36 , H01P1/38 , H01P5/12 , H01P5/18 , H01Q3/30 , H01Q21/0006 , H01Q21/0037 , H01Q21/22
摘要： As a layout requirement imposed on an in-phase corporate-feed circuit, there is provided only a layout requirement to equalize the electric length of a transmission line (4) between one of N T-branch units (6) which is m-th when counted from a start point of a path A, and another one of the T-branch units (6) which is (m+1)-th when counted from the start point of the path A, to that of a transmission line (8) between one of N T-branch units (10) which is m-th when counted from an end point of a path B, and another one of the T-branch units (10) which is (m+1)-th when counted from the end point of the path B. Therefore, the in-phase corporate-feed circuit can be formed in a space smaller than that in which its circuit configuration of tournament type is formed, and downsizing of the circuit size can be achieved.

6. 发明公开

EP2629424A1 FREQUENCY SYNTHESIZER 审中-公开
标题翻译：频率合成器
公开(公告)号：EP2629424A1
公开(公告)日：2013-08-21
申请号：EP11864036.6
申请日：2011-04-19
申请人： Mitsubishi Electric Corporation
发明人： TAJIMA, Kenichi , NAKAMIZO, Hideyuki , HIEDA, Morishige
IPC分类号： H03L7/087 , H03L7/08 , H03L7/085 , H03L7/095 , H03L7/197
CPC分类号： H03L7/087 , H03L7/085 , H03L7/113 , H03L7/197
摘要： A phase difference detecting circuit 3 includes a sync detecting circuit 21 for detecting establishment of phase sync from phase difference signals D and U generated by a D-type flip-flop 13, and a switch 22 for supplying, unless the sync detecting circuit 21 detects the establishment of the phase sync, the control voltage V t1 generated by the current-output-matching loop filter 15 to a voltage-controlled oscillator 4, and for supplying, when the sync detecting circuit 21 detects the establishment of the phase sync, the control voltage V t2 generated by the voltage-output-matching loop filter 20 to the voltage-controlled oscillator 4.
摘要翻译：相位差检测电路3包括用于检测由D型触发器13产生的相位差信号D和U建立相位同步的同步检测电路21和用于提供的开关22，除非同步检测电路21检测到相位同步的建立，由电流输出匹配环路滤波器15产生的控制电压Vt1到电压控制振荡器4，并且当同步检测电路21检测到相位同步的建立时，提供控制由电压输出匹配环路滤波器20生成的电压Vt2输出到电压控制振荡器4。

7. 发明公开

EP3683967A1 SIGNAL SOURCE 审中-公开
公开(公告)号：EP3683967A1
公开(公告)日：2020-07-22
申请号：EP17929219.8
申请日：2017-10-17
申请人： Mitsubishi Electric Corporation
发明人： WADA, Osamu , MIZUTANI, Hiroyuki , TAJIMA, Kenichi
IPC分类号： H03L7/08 , H03L7/091
摘要： Conventional signal sources each have a disadvantage that the noise in a control voltage of a VCO increases, thereby deteriorating the phase noise of an output signal of the signal source.
A signal source of the present invention includes: a reference signal source for outputting a reference signal; a phase frequency comparator for detecting a phase difference between the reference signal and an oscillation signal and outputting a signal corresponding to the phase difference; a filter for filtering the signal output by the phase frequency comparator; an oscillator for outputting the oscillation signal depending on the signal filtered by the filter; and an S/H circuit for receiving a clock signal for controlling a phase of the oscillation signal by controlling sampling operation and holding operation, sampling at least one of the oscillation signal and the reference signal in synchronization with the clock signal, and outputting at least one of the sampled reference signal and the sampled oscillation signal to the phase frequency comparator, the S/H circuit disposed between the oscillator and the phase frequency comparator or between the reference signal source and the phase frequency comparator.

8. 发明授权

EP2383887B1 MULTI-PORT AMPLIFIER AND WIRELESS DEVICE USING SAME 失效
公开(公告)号：EP2383887B1
公开(公告)日：2019-08-28
申请号：EP09837530.6
申请日：2009-10-01
申请人： Mitsubishi Electric Corporation
发明人： HANGAI, Masatake , MORI, Kazutomi , TAJIMA, Kenichi , TAHARA, Yukihiro , HIEDA, Morishige
IPC分类号： H03F3/189 , H03F1/32 , H03F3/24 , H03F3/68 , H04B1/04 , H04B1/08 , H03F3/60

9. 发明公开

EP3410602A1 PULSE SHIFT CIRCUIT AND FREQUENCY SYNTHESIZER 有权
公开(公告)号：EP3410602A1
公开(公告)日：2018-12-05
申请号：EP17762875.7
申请日：2017-02-20
申请人： Mitsubishi Electric Corporation
发明人： NAKAMIZO, Hideyuki , HIEDA, Morishige , MIZUTANI, Hiroyuki , TAJIMA, Kenichi
IPC分类号： H03L7/197 , H03L7/23 , H03M3/02
摘要： A problem with conventional distortion pulse shift circuits is that the output timing of a pulse signal cannot be controlled unless a reset signal is used. A pulse shift circuit according to the present invention includes: an integrator to integrate, for every clock, the first signal to be inputted; a quantizer to receive the second signal and to output a pulse signal when an integrated value of the integrator becomes equal to or larger than a signal value of the second signal; a delay circuit to delay the pulse signal; a converter disposed before or after the delay circuit to convert a signal value of the pulse signal into the signal value of the second signal; a subtractor to subtract the signal value of the pulse signal converted by the converter, from the signal value of the first signal to be inputted to the integrator; and an input signal control circuit to receive a third signal, to be disposed before the integrator, and to add a signal value corresponding to the third signal to the first signal to be inputted to the integrator or to block the first signal from being inputted to the integrator for clocks corresponding to the third signal.

10. 发明授权

EP1760876B1 VOLTAGE CONTROLLED OSCILLATOR 有权
公开(公告)号：EP1760876B1
公开(公告)日：2018-05-30
申请号：EP05720170.9
申请日：2005-03-07
申请人： MITSUBISHI ELECTRIC CORPORATION
发明人： TSURU, Masaomi , KAWAKAMI, Kenji , TAJIMA, Kenichi , MIYAZAKI, Moriyasu , MIYAMOTO, Kazuhiro , NAKANE, Masafumi
IPC分类号： H03B5/12 , H03H11/44 , H03H11/48
CPC分类号： H03H11/44 , H03B5/1203 , H03B5/1228 , H03B5/1231 , H03B5/1243 , H03B5/1293 , H03B2200/0042 , H03H11/28 , H03H11/481
摘要： A voltage-controlled oscillator has a tuned circuit for controlling the oscillation frequency. The tuned circuit has a variable-capacitance element whose capacitance varies in response to a control voltage and a negative capacitance circuit whose impedance frequency characteristics have opposite characteristics to those of a normal capacitance, and which is connected to the variable-capacitance element. The configuration enables increasing the variation ratio corresponding to the control voltage of the combined capacitance composed of the variable-capacitance element and negative capacitance circuit, thereby broadening the oscillation frequency band.

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