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    • 6. 发明公开
    • SILICON CARBIDE BIPOLAR SEMICONDUCTOR DEVICE
    • SILICIUMCARBID-BIPOLARHALBLEITERBAUELEMENT
    • EP1973165A4
    • 2009-09-02
    • EP06834573
    • 2006-12-13
    • KANSAI ELECTRIC POWER COCENTRAL RES INST ELECT
    • ISHII RYOSUKENAKAYAMA KOJISUGAWARA YOSHITAKAMIYANAGI TOSHIYUKITSUCHIDA HIDEKAZUKAMATA ISAHONAKAMURA TOMONORI
    • H01L29/861H01L21/04H01L29/06H01L29/24
    • H01L29/1604H01L21/0465H01L21/047H01L29/0615H01L29/0619H01L29/0661H01L29/1608H01L29/6606H01L29/66068H01L29/8613
    • A SiC bipolar semiconductor device having a mesa shape wherein a first conductivity type SiC drift layer and a second conductivity type SiC charge injection layer are epitaxially grown on the surface of a SiC single crystal substrate. In the SiC bipolar semiconductor device, generation and area increase of lamination defects are suppressed, and increase of a forward voltage is suppressed. Furthermore, withstand voltage characteristics are improved in the status where a reverse voltage is applied. On a mesa wall section or on the mesa wall section and a mesa peripheral section, a conduction deterioration preventing layer is formed for spatially separating the surface from a pn junction interface. In one embodiment, the conduction deterioration preventing layer is composed of a second conductivity type silicon carbide low resistance layer which becomes equipotential when a reverse voltage is applied. In another embodiment, the conduction deterioration preventing layer is composed of a second conductivity type silicon carbide conductive layer, and a metal film which becomes equipotential when a reverse voltage is applied is formed on the surface of the conduction deterioration preventing layer. Furthermore, in another embodiment, the conduction deterioration preventing layer is composed of a high resistance amorphous layer.
    • 一种具有台面形状的SiC双极型半导体器件,其中第一导电型SiC漂移层和第二导电型SiC电荷注入层在SiC单晶衬底的表面上外延生长。 在SiC双极型半导体器件中,抑制了层叠缺陷的产生和面积增加,并抑制了正向电压的增加。 此外,在施加反向电压的状态下耐电压特性得到改善。 在台面壁部分上或在台面壁部分和台面周边部分上,形成用于在空间上将表面与pn结界面分离的导电劣化防止层。 在一个实施例中,导通恶化防止层由当施加反向电压时变为等电位的第二导电类型碳化硅低电阻层组成。 在另一实施例中,导通恶化防止层由第二导电类型的碳化硅导电层构成,并且在导通恶化防止层的表面上形成当施加反向电压时变为等电位的金属膜。 此外,在另一个实施例中,导电劣化防止层由高电阻非晶层构成。
    • 9. 发明公开
    • GATE TURN-OFF THYRISTOR
    • GATE-AUSSCHALT晶闸管
    • EP1619724A4
    • 2008-11-12
    • EP04726292
    • 2004-04-07
    • KANSAI ELECTRIC POWER CO
    • ASANO KATSUNORISUGAWARA YOSHITAKA
    • H01L29/74H01L29/06H01L29/10H01L29/744
    • H01L29/1016H01L29/0615H01L29/0834H01L29/744
    • A mesa-type wide-gap semiconductor gate turn-off thyristor has a low gate withstand voltage and a large leakage current. Since the ionization rate of P-type impurities greatly increases at high temperatures when compared with that at room temperature, the hole implantation amount increases and the minority carrier lifetime becomes longer. Consequently, the maximum controllable current is significantly lowered when compared with that at room temperature. To solve these problems, a p-type base layer is formed on an n-type SiC cathode emitter layer which has a cathode electrode on one surface, and a thin n-type base layer is formed on the p-type base layer. A mesa-shaped p-type anode emitter layer is formed in the central region of the n-type base layer. An n-type gate contact region is formed sufficiently apart from the junction between the p-type anode emitter layer and the n-type base layer, and an n-type low-resistance gate region is so formed in the n-type base layer that it surrounds the anode emitter layer.
    • 台面型宽间隙半导体栅极关断晶闸管的栅极耐压低,漏电流大。 由于与室温相比,P型杂质的离子化率在高温下大幅增加,因此空穴注入量增加,少数载流子寿命变长。 因此,与室温下相比,最大可控电流显着降低。 为了解决这些问题,在一个面上具有阴极电极的n型SiC阴极发射极层上形成p型基极层,在该p型基极层上形成薄的n型基极层。 台面形p型阳极发射极层形成在n型基极层的中心区域中。 形成与p型阳极发射极层和n型基极层之间的结足够远的n型栅极接触区,并且在n型基极层中形成n型低电阻栅极区 它围绕阳极发射极层。