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1. 发明公开

EP0382699A2 Interprocessor data transfer system and method 失效
标题翻译：系统和Verfahren zurDatenübertragungzwischen Prozessoren。
公开(公告)号：EP0382699A2
公开(公告)日：1990-08-16
申请号：EP90850052.3
申请日：1990-02-06
申请人： International Business Machines Corporation
发明人： Nuechterlein, David William , Rinaldi, Mark Anthony
IPC分类号： G06F15/16 , G06F5/06
CPC分类号： G06F5/10 , G06F15/167
摘要： A system and method for managing a FIFO queue to allow tentative enqueuing of data entities. Additional memory pointers and control logic are provided to allow data entries to be added to a FIFO queue conditionally. Combinatorial logic allows the FIFO queue to be managed so that the tentative or conditional data entries may be purged as a group, committed or made permanent as a group. This system allows an increase in pipeline processor information transfer when several data entities to be transferred are related and the commitment to transfer the group cannot be made until after one or more of the group of data entities have been processed. Selector control are provided so that a system developer can implement management schemes to ensure that the desired function is implemented.
摘要翻译：一种用于管理FIFO队列以允许暂时排入数据实体的系统和方法。提供了附加的存储器指针和控制逻辑以允许有条件地将数据条目添加到FIFO队列中。组合逻辑允许对FIFO队列进行管理，以使临时条件或条件数据条目可以被清除为一组，被提交或作为一个组成永久的组。当要传送的几个数据实体相关时，该系统允许流水线处理器信息传送的增加，并且直到一组或多个数据实体被处理之后才能进行转移的承诺。提供选择器控制，使得系统开发人员可以实现管理方案，以确保实现所需的功能。

2. 发明授权

EP0314342B1 Parallel pipelined computer processor 失效
标题翻译：并行流水线计算机。
公开(公告)号：EP0314342B1
公开(公告)日：1995-03-08
申请号：EP88309574.7
申请日：1988-10-13
申请人： International Business Machines Corporation
发明人： Nuechterlein, David William , Rinaldi, Mark Anthony
IPC分类号： G06F15/76
CPC分类号： G06F15/8092 , G06F15/8007

3. 发明公开

EP0314342A3 Parallel pipelined computer processor 失效
标题翻译：并行管道计算机处理器
公开(公告)号：EP0314342A3
公开(公告)日：1990-10-17
申请号：EP88309574.7
申请日：1988-10-13
申请人： International Business Machines Corporation
发明人： Nuechterlein, David William , Rinaldi, Mark Anthony
IPC分类号： G06F15/76
CPC分类号： G06F15/8092 , G06F15/8007
摘要： A processor adapted for parallel and/or pipelined interconnection with other like processors. An arithmetic logic unit has associated with it an output FIFO register stack having output data lines capable of parallel connection with the output data lines of other such processors, such output stack being loadable with a predetermined neutral value such that when said neutral value is present at their output data lines it permits the data present at the output lines of another such processor connected in parallel therewith to control the output data bus. The invention eliminates the need to have control over several such processors connected in parallel and/or pipelined configuration by way of external arbitration logic.

4. 发明公开

EP0653742A3 Device for scaling real-time image frames in multi-media workstations 失效
标题翻译：一种在多媒体作品图像的实时缩放装置。
公开(公告)号：EP0653742A3
公开(公告)日：1995-09-06
申请号：EP94480107.5
申请日：1994-10-26
申请人： International Business Machines Corporation
发明人： Dwin, David Ronny , Lee, William Robert , Nuechterlein, David William , Pennisi, Joseph Michael , Yosim, Paul Stewart
IPC分类号： G09G5/00
CPC分类号： G09G5/00 , G06T3/40 , G09G2340/125 , H04N9/641
摘要： An adapter for use in a multi-media workstation includes a device (24) which accepts real-time video information at a first size, reduces the size to a selected one of a plurality of available sizes and places the reduced real-time video information into a selected area of the video memory (18) of a computer graphic display device (22). Thereafter, the scaled real-time video information is displayed with other computer graphics applications, in a sub-window of the screen of the display device.

5. 发明公开

EP0549508A1 Reconfigurable multi-way associative cache memory 失效
标题翻译： Rekonfigurierbarer Mehrweg-assoziativer Cachespeicher。
公开(公告)号：EP0549508A1
公开(公告)日：1993-06-30
申请号：EP92480180.6
申请日：1992-11-30
申请人： International Business Machines Corporation
发明人： Coyle, William Edward , Nuechterlein, David William , O'Donnell, Kim Edward , Sartorius, Thomas Andrew , Schultz, Kenneth David , Wolters, Emmy Marion
IPC分类号： G06F12/08
CPC分类号： G06F12/0864 , G06F2212/601
摘要： A reconfigurable set associative cache memory can be reconfigured from 2x way to 2y way set associative cache memory by effectively merging a predetermined number of least significant bits of the tag field of the main memory address with the line field of the main memory address. The effective merging is provided by logically merging least significant bits of the tag field with a reconfiguration designation. As a result, Y-X+1 different configurations of cache memory can be obtained using the Y-X least significant bits of the tag field merged with the cache memory address.
摘要翻译：通过将主存储器地址的标签字段的预定数量的最低有效位与主存储器地址的行字段有效地合并，可重配置集合相关高速缓冲存储器可以通过从2x路向2y集合关联高速缓冲存储器重新配置。通过将标签字段的最低有效位与重新配置指定逻辑合并来提供有效合并。结果，可以使用与高速缓存存储器地址合并的标签字段的Y-X最低有效位来获得高速缓冲存储器的Y-X + 1不同配置。

6. 发明公开

EP0653742A2 Device for scaling real-time image frames in multi-media workstations 失效
标题翻译：用于在多媒体工作站中缩放实时图像帧的设备
公开(公告)号：EP0653742A2
公开(公告)日：1995-05-17
申请号：EP94480107.5
申请日：1994-10-26
申请人： International Business Machines Corporation
发明人： Dwin, David Ronny , Lee, William Robert , Nuechterlein, David William , Pennisi, Joseph Michael , Yosim, Paul Stewart
IPC分类号： G09G5/00
CPC分类号： G09G5/00 , G06T3/40 , G09G2340/125 , H04N9/641
摘要： An adapter for use in a multi-media workstation includes a device (24) which accepts real-time video information at a first size, reduces the size to a selected one of a plurality of available sizes and places the reduced real-time video information into a selected area of the video memory (18) of a computer graphic display device (22). Thereafter, the scaled real-time video information is displayed with other computer graphics applications, in a sub-window of the screen of the display device.
摘要翻译：用于多媒体工作站的适配器包括接收第一尺寸的实时视频信息的设备（24），将尺寸缩小到多个可用尺寸中的选定尺寸并将缩小的实时视频信息进入计算机图形显示设备（22）的视频存储器（18）的选定区域。之后，缩放的实时视频信息与其他计算机图形应用一起显示在显示设备的屏幕的子窗口中。

7. 发明公开

EP0382699A3 Interprocessor data transfer system and method 失效
标题翻译：交互式数据传输系统和方法
公开(公告)号：EP0382699A3
公开(公告)日：1992-07-15
申请号：EP90850052.3
申请日：1990-02-06
申请人： International Business Machines Corporation
发明人： Nuechterlein, David William , Rinaldi, Mark Anthony
IPC分类号： G06F15/16 , G06F5/06
CPC分类号： G06F5/10 , G06F15/167
摘要： A system and method for managing a FIFO queue to allow tentative enqueuing of data entities. Additional memory pointers and control logic are provided to allow data entries to be added to a FIFO queue conditionally. Combinatorial logic allows the FIFO queue to be managed so that the tentative or conditional data entries may be purged as a group, committed or made permanent as a group. This system allows an increase in pipeline processor information transfer when several data entities to be transferred are related and the commitment to transfer the group cannot be made until after one or more of the group of data entities have been processed. Selector control are provided so that a system developer can implement management schemes to ensure that the desired function is implemented.

8. 发明公开

EP0314342A2 Parallel pipelined computer processor 失效
标题翻译：平行的Pipelinerechner。
公开(公告)号：EP0314342A2
公开(公告)日：1989-05-03
申请号：EP88309574.7
申请日：1988-10-13
申请人： International Business Machines Corporation
发明人： Nuechterlein, David William , Rinaldi, Mark Anthony
IPC分类号： G06F15/76
CPC分类号： G06F15/8092 , G06F15/8007
摘要： A processor adapted for parallel and/or pipelined interconnection with other like processors. An arithmetic logic unit has associated with it an output FIFO register stack having output data lines capable of parallel connection with the output data lines of other such processors, such output stack being loadable with a predetermined neutral value such that when said neutral value is present at their output data lines it permits the data present at the output lines of another such processor connected in parallel therewith to control the output data bus. The invention eliminates the need to have control over several such processors connected in parallel and/or pipelined configuration by way of external arbitration logic.
摘要翻译：适于与其他类似处理器并行和/或流水线互连的处理器。算术逻辑单元与其相关联，具有能够与其他这样的处理器的输出数据线并联的输出数据线的输出FIFO寄存器堆栈，这样的输出堆栈可以预定的中性值加载，使得当所述中性值存在于它们的输出数据线允许存在于并行连接的另一个这样的处理器的输出线上的数据来控制输出数据总线。本发明消除了通过外部仲裁逻辑控制并联和/或流水线配置的几个这样的处理器的需要。

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