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1. 发明公开

EP1479103A1 METHOD OF CREATING HIGH-QUALITY RELAXED SiGe-ON-INSULATOR FOR STRAINED Si CMOS APPLICATIONS 审中-公开
标题翻译：用于生产高质量的弛豫SiGe-ON-绝缘子应变硅CMOS应用
公开(公告)号：EP1479103A1
公开(公告)日：2004-11-24
申请号：EP03731957.1
申请日：2003-01-16
申请人： International Business Machines Corporation
发明人： BEDELL, Stephen, W. , CHU, Jack, O. , FOGEL, Keith, E. , KOESTER, Stephen, J. , SADANA, Devendra, K. , OTT, John, Albrecht,37 Lindon Avenue
IPC分类号： H01L21/331
CPC分类号： H01L21/76243 , H01L21/02378 , H01L21/02381 , H01L21/02488 , H01L21/02532 , H01L21/02612 , H01L21/2251 , H01L21/324 , H01L27/1203 , H01L29/66916 , Y10S438/938 , Y10T428/12674 , Y10T428/265 , Y10T428/31848
摘要： A method of forming a thin, high-quality relaxed SiGe-on-insulator substrate (10) material is provided which first includes forming a SiGe or pure Ge layer on a surface of a first single crystal Si layer (14) which is present atop a barrier layer (12) that is resistant to the diffusion of Ge. Optionally forming a Si cap layer (18) over the SiGe or pure Ge layer (16), and thereafter heating the various layers at a temperature which permits interdiffusion of Ge throughtout the first single crystal Si layer (14), the optional Si cap (18) and the SiGe or pure Ge layer (16) thereby forming a substantially relaxed, single crystal SiGe layer atop the barrier layer (12). Additional SiGe regrowth and/or formation of a strained epi-Si layer may follow the above steps. SiGe-on-insulator substrate materials as well as structures including at least the SiGe-on-insulator substrate material are also disclosed herein.

2. 发明公开

EP1483783A2 STRAINED SI BASED LAYER MADE BY UHV-CVD; AND DEVICES THEREIN 审中-公开
标题翻译： BY UHV-CVD产生的电压硅层上BASE及有关安排
公开(公告)号：EP1483783A2
公开(公告)日：2004-12-08
申请号：EP03707710.4
申请日：2003-02-04
申请人： International Business Machines Corporation
发明人： CHU, Jack, O. , ISMAIL, Khaled,Apt. 21
IPC分类号： H01L21/20 , H01L21/762 , H01L27/00
CPC分类号： H01L29/78654 , H01L21/02381 , H01L21/0245 , H01L21/02505 , H01L21/0251 , H01L21/02532 , H01L21/02664 , H01L21/76256 , H01L21/76259 , H01L29/66916 , H01L29/78603
摘要： A method for fabricating a strained Si based layer, devices manufactured in this layer, and electronic systems comprising such layers and devices are disclosed. The method comprises the steps of growing epitaxially a SiGe layer on a substrate, and creating a varying Ge concentration in this SiGe layer. The Ge concentration in the SiGe layer includes a unique Ge overshoot zone, where the Ge concentration is abruptly and significantly increased. The Si based layer is epitaxially deposited onto the SiGe layer, whereby is becomes tensilely strained. It is also disclosed that the strained Si based layer, typically Si or SiGe, can be transferred to a different bulk substrate, or to an insulator.

3. 发明公开

EP1570511A2 RELAXED SiGe LAYERS ON Si OR SILICON-ON-INSULATOR SUBSTRATES BY ION IMPLANTATION AND THERMAL ANNEALING 审中-公开
标题翻译：松弛SiGe LAYERS ON SI或硅 - 绝缘体上通过离子注入和热处理
公开(公告)号：EP1570511A2
公开(公告)日：2005-09-07
申请号：EP03786848.6
申请日：2003-11-19
申请人： International Business Machines Corporation
发明人： CHRISTIANSEN, Silke H. , CHU, Jack, O. , GRILL, Alfred , MOONEY, Patricia, M.
IPC分类号： H01L21/302 , H01L21/461
CPC分类号： H01L21/26506 , H01L21/02378 , H01L21/02381 , H01L21/02532 , H01L21/02664 , H01L21/02667 , H01L21/02694 , H01L21/7624 , H01L21/76251 , Y10S438/933
摘要： A method to obtain thin (less than 300 nm) strain-relaxed Si1-xGex buffer layers on Si or silicon-on-insulator (SOI) substrates. These buffer layers have a homogeneous distribution of misfit dislocations that relieve the strain, remarkably smooth surfaces, and a low threading dislocation (TD) density, i.e. less than 10 cm . The approach begins with the growth of a pseudomorphic or nearly pseudomorphic Si1-xGex layer, i.e., a layer that is free of misfit dislocations, which is then implanted with He or other light elements and subsequently annealed to achieve the substantial strain relaxation. The very effective strain relaxation mechanism operating with this method is dislocation nucleation at He-induced platelets (not bubbles) that lie below the Si/Si1-xGex interface, parallel to the Si(001) surface.

4. 发明公开

EP1169737A1 HIGH SPEED GE CHANNEL HETEROSTRUCTURES FOR FIELD EFFECT DEVICES 有权
标题翻译：随着高速FOR场效应安排GE通道异质结构
公开(公告)号：EP1169737A1
公开(公告)日：2002-01-09
申请号：EP00914903.0
申请日：2000-03-11
申请人： International Business Machines Corporation
发明人： CHU, Jack, O.
IPC分类号： H01L29/778
CPC分类号： H01L29/7782
摘要： A method and a layered heterostructure for forming high mobility Ge channel field effect transistors is described incorporating a plurality of semiconductor layers on a semiconductor substrate, and a channel structure of a compressively strained epitaxial Ge layer having a higher barrier or a deeper confining quantum well and having extremely high hole mobility for complementary MODFETs and MOSFETs. The invention overcomes the problem of a limited hole mobility due to alloy scattering for a p-channel device with only a single compressively strained SiGe channel layer. This invention further provides improvements in mobility and transconductance over deep submicron state-of-the art Si pMOSFETs in addition to having a broad temperature operation regime from above room temperature (425 K) down to cryogenic low temperatures (0.4 K) where at low temperatures even high device performances are achievable.

5. 发明授权

EP1169737B1 HIGH SPEED GE CHANNEL HETEROSTRUCTURES FOR FIELD EFFECT DEVICES 有权
标题翻译：随着高速FOR场效应安排GE通道异质结构
公开(公告)号：EP1169737B1
公开(公告)日：2008-05-07
申请号：EP00914903.0
申请日：2000-03-11
申请人： International Business Machines Corporation
发明人： CHU, Jack, O.
IPC分类号： H01L29/778
CPC分类号： H01L29/7782
摘要： A method and a layered heterostructure for forming high mobility Ge channel field effect transistors is described incorporating a plurality of semiconductor layers on a semiconductor substrate, and a channel structure of a compressively strained epitaxial Ge layer having a higher barrier or a deeper confining quantum well and having extremely high hole mobility for complementary MODFETs and MOSFETs. The invention overcomes the problem of a limited hole mobility due to alloy scattering for a p-channel device with only a single compressively strained SiGe channel layer. This invention further provides improvements in mobility and transconductance over deep submicron state-of-the art Si pMOSFETs in addition to having a broad temperature operation regime from above room temperature (425 K) down to cryogenic low temperatures (0.4 K) where at low temperatures even high device performances are achievable.

6. 发明授权

EP1728283B1 STRUCTURE FOR AND METHOD OF FABRICATING A HIGH-SPEED CMOS-COMPATIBLE GE-ON-INSULATOR PHOTODETECTOR 有权转让
标题翻译：一种高速CMOS兼容绝缘栅双极型晶体管的结构和制造方法
公开(公告)号：EP1728283B1
公开(公告)日：2007-06-13
申请号：EP05723468.4
申请日：2005-02-22
申请人： International Business Machines Corporation
发明人： CHU, Jack, O. , DEHLINGER, Gabriel, K. , GRILL, Alfred , KOESTER, Steven, J. , OUYANG, Qiging , SCHAUB, Jeremy, D., c/o IBM U.K. Ltd.
IPC分类号： H01L31/101
CPC分类号： H01L31/101
摘要： The invention addresses the problem of creating a high-speed, high-efficiency photodetector that is compatible with Si CMOS technology. The structure consists of a Ge absorbing layer on a thin SOI substrate, and utilizes isolation regions, alternating n-and p-type contacts, and low-resistance surface electrodes. The device achieves high bandwidth by utilizing a buried insulating layer to isolate carriers generated in the underlying substrate, high quantum efficiency over a broad spectrum by utilizing a Ge absorbing layer, low voltage operation by utilizing thin a absorbing layer and narrow electrode spacings, and compatibility with CMOS devices by virtue of its planar structure and use of a group IV absorbing material. The method for fabricating the photodetector uses direct growth of Ge on thin SOI or an epitaxial oxide, and subsequent thermal annealing to achieve a high-quality absorbing layer. This method limits the amount of Si available for interdiffusion, thereby allowing the Ge layer to be annealed without causing substantial dilution of the Ge layer by the underlying Si.
摘要翻译：本发明解决了创建与Si CMOS技术兼容的高速，高效率光电探测器的问题。该结构由薄SOI衬底上的Ge吸收层组成，并利用隔离区，交替的n型和p型触点以及低电阻表面电极。该器件利用掩埋绝缘层隔离底层衬底中产生的载流子，通过利用Ge吸收层在广谱上获得高量子效率，利用薄吸收层和窄电极间距实现低电压操作，以及兼容性凭借其平面结构和使用IV族吸收材料而具有CMOS器件。用于制造光电检测器的方法使用在薄SOI或外延氧化物上直接生长Ge，并且随后进行热退火以实现高质量的吸收层。该方法限制了可用于相互扩散的Si的量，由此允许Ge层退火而不会导致Ge层基本上被下面的Si稀释。

7. 发明授权

EP1728283B9 STRUCTURE FOR AND METHOD OF FABRICATING A HIGH-SPEED CMOS-COMPATIBLE GE-ON-INSULATOR PHOTODETECTOR 有权转让
标题翻译：结构与方法生产CMOS兼容的HIGH-SPEED GE-ON - 绝缘体 - 光检测器
公开(公告)号：EP1728283B9
公开(公告)日：2007-10-03
申请号：EP05723468.4
申请日：2005-02-22
申请人： International Business Machines Corporation
发明人： CHU, Jack, O. , DEHLINGER, Gabriel, K. , GRILL, Alfred , KOESTER, Steven, J. , OUYANG, Qiging , SCHAUB, Jeremy, D., c/o IBM U.K. Ltd.
IPC分类号： H01L31/101
CPC分类号： H01L31/101
摘要： The invention addresses the problem of creating a high-speed, high-efficiency photodetector that is compatible with Si CMOS technology. The structure consists of a Ge absorbing layer on a thin SOI substrate, and utilizes isolation regions, alternating n-and p-type contacts, and low-resistance surface electrodes. The device achieves high bandwidth by utilizing a buried insulating layer to isolate carriers generated in the underlying substrate, high quantum efficiency over a broad spectrum by utilizing a Ge absorbing layer, low voltage operation by utilizing thin a absorbing layer and narrow electrode spacings, and compatibility with CMOS devices by virtue of its planar structure and use of a group IV absorbing material. The method for fabricating the photodetector uses direct growth of Ge on thin SOI or an epitaxial oxide, and subsequent thermal annealing to achieve a high-quality absorbing layer. This method limits the amount of Si available for interdiffusion, thereby allowing the Ge layer to be annealed without causing substantial dilution of the Ge layer by the underlying Si.

8. 发明公开

EP1728283A2 STRUCTURE FOR AND METHOD OF FABRICATING A HIGH-SPEED CMOS-COMPATIBLE GE-ON-INSULATOR PHOTODETECTOR 有权转让
标题翻译：结构与方法生产CMOS兼容的HIGH-SPEED GE-ON - 绝缘体 - 光检测器
公开(公告)号：EP1728283A2
公开(公告)日：2006-12-06
申请号：EP05723468.4
申请日：2005-02-22
申请人： International Business Machines Corporation
发明人： CHU, Jack, O. , DEHLINGER, Gabriel, K. , GRILL, Alfred , KOESTER, Steven, J. , OUYANG, Qiging , SCHAUB, Jeremy, D.
IPC分类号： H01L31/101
CPC分类号： H01L31/101
摘要： The invention addresses the problem of creating a high-speed, high-efficiency photodetector that is compatible with Si CMOS technology. The structure consists of a Ge absorbing layer on a thin SOI substrate, and utilizes isolation regions, alternating n-and p-type contacts, and low-resistance surface electrodes. The device achieves high bandwidth by utilizing a buried insulating layer to isolate carriers generated in the underlying substrate, high quantum efficiency over a broad spectrum by utilizing a Ge absorbing layer, low voltage operation by utilizing thin a absorbing layer and narrow electrode spacings, and compatibility with CMOS devices by virtue of its planar structure and use of a group IV absorbing material. The method for fabricating the photodetector uses direct growth of Ge on thin SOI or an epitaxial oxide, and subsequent thermal annealing to achieve a high-quality absorbing layer. This method limits the amount of Si available for interdiffusion, thereby allowing the Ge layer to be annealed without causing substantial dilution of the Ge layer by the underlying Si.

9. 发明公开

EP1685590A2 ULTRA HIGH-SPEED SI/SIGE MODULATION-DOPED FIELD EFFECT TRANSISTORS ON ULTRA THIN SOI/SGOI SUBSTRATE 审中-公开
标题翻译：超快速调制掺杂SI / SIGE场效应晶体管ON超薄SOI / SGOI SUBSTRATE
公开(公告)号：EP1685590A2
公开(公告)日：2006-08-02
申请号：EP04809631.7
申请日：2004-08-27
申请人： International Business Machines Corporation
发明人： CHU, Jack, O. , OUYANG, Qiqing, C.
IPC分类号： H01L21/335 , H01L29/10 , H01L29/778 , H01L29/786
CPC分类号： H01L29/1054 , H01L29/78687
摘要： A silicon and silicon germanium based semiconductor MODFET device design and method of manufacture. The MODFET design includes a high-mobility layer structure capable of ultra high-speed, low-noise for a variety of communication applications including RF, microwave, sub-millimeter-wave and millimeter-wave. The epitaxial field effect transistor layer structure includes critical (vertical and lateral) device scaling and layer structure design for a high mobility strained n-channel and p-channel transistor incorporating silicon and silicon germanium layers to form the optimum modulation-doped heterostructure on an ultra thin SOI or SGOI substrate capable of achieving greatly improved RF performance.

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