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1. 发明公开

EP4220405A1 WORKLOAD SCHEDULING AND DISTRIBUTION ON A DISTRIBUTED GRAPHICS DEVICE 审中-实审
公开(公告)号：EP4220405A1
公开(公告)日：2023-08-02
申请号：EP23169476.1
申请日：2019-10-22
申请人： Intel Corporation
发明人： Vembu, Balaji , Fliflet, Brandon , Valerio, James , Apodaca, Michael , Ashbaugh, Ben , Nalluri, Hema , Shah, Ankur , Ramadoss, Murali , Puffer, David , Navale, Aditya , Appu, Abhishek , Ray, Joydeep , Schluessler, Travis
IPC分类号： G06F9/50
摘要： Embodiments described herein provide a graphics, media, and compute device having a tiled architecture composed of a number of tiles of smaller graphics devices. The work distribution infrastructure for such device enables the distribution of workloads across multiple tiles of the device. Work items can be submitted to any one or more of the multiple tiles, with workloads able to span multiple tiles. Additionally, upon completion of a work item, graphics, media, and/or compute engines within the device can readily acquire new work items for execution with minimal latency.

2. 发明公开

EP3964958A1 COMPUTE OPTIMIZATION MECHANISM FOR DEEP NEURAL NETWORKS 无效
公开(公告)号：EP3964958A1
公开(公告)日：2022-03-09
申请号：EP21205193.2
申请日：2018-03-23
申请人： Intel Corporation
发明人： Surti, Prasoonkumar , Srinivasa, Narayan , Chen, Feng , Ray, Joydeep , Ashbaugh, Ben J. , Galoppo von Borries, Nicolas , Nurvitadhi, Eriko , Vembu, Balaji , Lin, Tsung-Han , Sinha, Kamal , Barik, Rajkishore , Baghsorkhi, Sara S. , Gottschlich, Justin E. , Koker, Altug , Satish, Nadathur Rajagopalan , Akhbari, Farshad , Kim, Dukhwan , Fu, Wenyin , Schluessler, Travis T. , Mastronarde, Josh B. , Hurd, Linda L. , Feit, John H. , Boles, Jeffery S. , Lake, Adam T. , Vaidyanathan, Karthik , Burke, Devan , Maiyuran, Subramaniam , Appu, Abhishek R.
IPC分类号： G06F9/50 , G06F8/41 , G06T1/20 , G06F9/455 , G06N3/04 , G06N3/08 , G06N3/063
摘要： The present disclosure provides a graphics processing unit comprising one or more multiprocessors, at least one of the one or more multiprocessors including a register file to store a plurality of different types of operands and a plurality of processing units, including a first set of execution units of a first type to process matrix instructions on a first set of operands stored in a first set of registers of the register file, wherein the first set of operands including one or more 64-bit operands and a second set of execution units of a second type, the second set of execution units being different from the first set of execution units, the second set of execution units to perform general purpose graphics processing unit, GPGPU, instructions on a second set of operands stored in a second set of registers of the register file.

3. 发明公开

EP3882769A1 EFFICIENT THREAD GROUP SCHEDULING 审中-公开
公开(公告)号：EP3882769A1
公开(公告)日：2021-09-22
申请号：EP21166927.0
申请日：2018-03-15
申请人： Intel Corporation
发明人： Ray, Joydeep , Appu, Abhishek R. , Koker, Altug , Sinah, Kamal , Vembu, Balaji , Barik, Raykishore , Nurvitadhi, Eriko , Galoppo von Borries, Nicolas C. , Lin, Tsung-Han , Jahagirdar, Sanjeev , Ranganathan, Vasanth
IPC分类号： G06F9/48
摘要： A mechanism is described for facilitating intelligent thread scheduling at autonomous machines. A method of embodiments, as described herein, includes detecting dependency information relating to a plurality of threads corresponding to a plurality of workloads associated with tasks relating to a processor including a graphics processor. The method may further include generating a tree of thread groups based on the dependency information, where each thread group includes multiple threads, and scheduling one or more of the thread groups associated a similar dependency to avoid dependency conflicts.

4. 发明公开

EP2075725A3 Securing content for playback 审中-公开
标题翻译：确保对播放内容
公开(公告)号：EP2075725A3
公开(公告)日：2012-05-09
申请号：EP08254134.3
申请日：2008-12-23
申请人： Intel Corporation
发明人： Vembu, Balaji , Sreenivas, Aditya , Gandhi, Wishwesh
IPC分类号： G06F21/00
CPC分类号： G06F21/84 , G06F21/10 , G06F21/74
摘要： A graphics engine may include a decryption device, a renderer, and a sprite or overlay engine, all connected to a display. A memory may have a protected and non-protected portions in one embodiment. An application may store encrypted content on the non-protected portion of said memory. The decryption device may access the encrypted material, decrypt the material, and provide it to the renderer engine of a graphics engine. The graphics engine may then process the decrypted material using the protected portion of the memory. Only graphics devices can access the protected portion of the memory in at least one mode, preventing access by outside sources. In addition, the protected memory may be stolen memory that is not identified to the operating system, making that stolen memory inaccessible to applications running on the operating system.

5. 发明公开

EP2107486A2 Method and apparatus for providing a secure display window inside the primary display 有权
标题翻译：用于在主显示器上提供一个安全显示窗口的方法和装置
公开(公告)号：EP2107486A2
公开(公告)日：2009-10-07
申请号：EP09250989.2
申请日：2009-03-31
申请人： Intel Corporation
发明人： Vembu, Balaji , Sarangdhar, Nitin , Shanbhogue, Vedvyas
IPC分类号： G06F21/00
CPC分类号： G06F21/606 , G06F21/10 , G06F21/84 , G06F2221/0735
摘要： In some embodiments, the invention involves securing sensitive data from malware on a computing platform and, more specifically, to utilizing virtualization technology and protected audio video path technologies to prohibit a user environment from directly accessing unencrypted sensitive data. In an embodiment a service operating system (SOS) accesses sensitive data requested by an application running in a user environment virtual machine, or a capability operating system (COS). The SOS application encrypts the sensitive data before passing the data to the COS. The COS makes requests directly to a graphics engine which decrypts the data before displaying the sensitive data on a display monitor. Other embodiments are described and claimed.
摘要翻译：在一些实施方案中，本发明包括在计算平台上保护免受恶意软件的敏感数据，并且更具体地，涉及利用虚拟化技术和受保护音频视频路径技术来阻止用户environmentsfrom直接访问未加密敏感数据。在服务操作系统（SOS）的实施方式的访问在用户环境中的虚拟机通过在应用程序的运行请求的敏感数据或能力操作系统（COS）。的SOS应用程序的数据传递到COS之前加密敏感数据。的COS使得直接请求到一个显示监视器上显示敏感数据之前哪个解密数据的图形引擎。其他实施例中描述并要求保护。

6. 发明公开

EP3955203A2 COORDINATION AND INCREASED UTILIZATION OF GRAPHICS PROCESSORS DURING INFERENCE 有权
公开(公告)号：EP3955203A2
公开(公告)日：2022-02-16
申请号：EP21181091.6
申请日：2018-03-02
申请人： INTEL Corporation
发明人： Appu, Abhishek R. , Koker, Altug , Weast, John C. , MacPherson, Mike B. , Hurd, Linda L. , Baghsorkhi, Sara S. , Gottschlich, Justin E. , Surti, Prasoonkumar , Sakthivel, Chandrasekaran , Ma, Liwei , Ould-Ahmed-Vall, ElMoustapha , Sinha, Kamal , Ray, Joydeep , Vembu, Balaji , Jahagirdar, Sanjeev , Ranganathan, Vasanth , Kim, Dukhwan
IPC分类号： G06T1/20
摘要： A method of embodiments, as described herein, includes scheduling resources in a system for a plurality of contexts, the resources of the system including multiple streaming processors; specifying a portion of available threads as a limitation on usage of the multiple streaming processors; and upon determining that the limitation on usage of the multiple streaming processors is set, limiting usage of the multiple streaming processors by one or more contexts of the plurality of contexts. Limiting usage of the multiple streaming processors includes limiting threads for the one or more contexts to the specified portion of available threads of the multiple streaming processors, the specified portion being less than all available threads of the multiple streaming processors. Limiting threads for the one or more contexts to the specified portion of available threads includes limiting the one or more contexts to a subset of the multiple streaming processors, the subset being less than all available streaming processors.

7. 发明公开

EP3680774A1 WORKLOAD SCHEDULING AND DISTRIBUTION ON A DISTRIBUTED GRAPHICS DEVICE 有权
公开(公告)号：EP3680774A1
公开(公告)日：2020-07-15
申请号：EP19204510.2
申请日：2019-10-22
申请人： Intel Corporation
发明人： Vembu, Balaji , Fliflet, Brandon , Valerio, James , Apodaca, Michael , Ashbaugh, Ben , Nalluri, Hema , Shah, Ankur , Ramadoss, Murali , Puffer, David , Navale, Aditya , Appu, Abhishek , Ray, Joydeep , Schluessler, Travis
IPC分类号： G06F9/50
摘要： Embodiments described herein provide a graphics, media, and compute device having a tiled architecture composed of a number of tiles of smaller graphics devices. The work distribution infrastructure for such device enables the distribution of workloads across multiple tiles of the device. Work items can be submitted to any one or more of the multiple tiles, with workloads able to span multiple tiles. Additionally, upon completion of a work item, graphics, media, and/or compute engines within the device can readily acquire new work items for execution with minimal latency.

8. 发明公开

EP3637246A1 INSTRUCTIONS AND LOGIC TO PERFORM FLOATING-POINT AND INTEGER OPERATIONS FOR MACHINE LEARNING 有权
公开(公告)号：EP3637246A1
公开(公告)日：2020-04-15
申请号：EP19214143.0
申请日：2018-03-26
申请人： INTEL Corporation
发明人： Kaul, Himanshu , Anders, Mark A. , Mathew, Sanu K. , Yao, Anbang , Ray, Joydeep , Tang, Ping T. , Strickland, Michael S. , Chen, Xiaoming , Shpeisman, Tatiana , Appu, Abhishek R. , Koker, Altug , Sinha, Kamal , Vembu, Balaji , Nurvitadhi, Eriko , Barik, Rajkishore , Lin, Tsung-Han , Ranganathan, Vasanth , Jahagirdar, Sanjeev , Galoppo Von Borries, Nicolas C.
IPC分类号： G06F7/483 , G06F7/544 , G06F9/30 , G06N3/04 , G06N3/063 , G06N3/08
摘要： One embodiment provides for a machine-learning hardware accelerator comprising a compute unit having an adder and a multiplier that are shared between integer data path and a floating-point datapath, the upper bits of input operands to the multiplier to be gated during floating-point operation.

9. 发明公开

EP4379648A3 MACHINE LEARNING SPARSE COMPUTATION MECHANISM 审中-实审
公开(公告)号：EP4379648A3
公开(公告)日：2024-09-11
申请号：EP24171188.6
申请日：2018-03-08
申请人： INTEL Corporation
发明人： Nurvitadhi, Eriko , Vembu, Balaji , Lin, Tsung-Han , Sinha, Kamal , Barik, Rajkishore , Galoppo von Borries, Nicolas
IPC分类号： G06N3/0442 , G06N3/0464 , G06N3/048 , G06N3/063 , G06N3/084 , G06N3/09 , G06T1/20
CPC分类号： G06F12/0811 , G06F12/0815 , G06F12/0831 , G06F12/0888 , G06F2212/102420130101 , G06F2212/30220130101 , G06F2212/62120130101 , G06F2212/40120130101 , G06T1/20 , G06N3/063 , G06N3/084 , Y02D10/00 , G06N3/0464 , G06N3/048 , G06N3/09 , G06N3/0442
摘要： A method and a data processing system for performing operations of a machine learning framework to facilitate a sparse matrix multiplication for convolutional layers are disclosed. Therefore, one or more primitives for enabling a compute kernel to specify one or more operations to be performed by the compute kernel of a graphics processor on an output of a sparse matrix multiplication operation are provided, the one or more operations including applying an activation function and the compute kernel being associated with the convolutional layers. An execution of the compute kernel to execute the sparse matrix multiplication operation on matrices relating to the convolutional layers and an execution of the compute kernel to apply the activation function to the output of the sparse matrix multiplication operation based on the one or more primitives are triggered.

10. 发明公开

EP4130976A1 INSTRUCTIONS AND LOGIC TO PERFORM FLOATING-POINT AND INTEGER OPERATIONS FOR MACHINE LEARNING 审中-公开
公开(公告)号：EP4130976A1
公开(公告)日：2023-02-08
申请号：EP22198967.6
申请日：2018-03-26
申请人： INTEL Corporation
发明人： Kaul, Himanshu , Anders, Mark A. , Mathew, Sanu K. , Yao, Anbang , Ray, Joydeep , Tang, Ping T. , Strickland, Michael S. , Chen, Xiaoming , Appu, Abhishek R. , Koker, Altug , Sinha, Kamal , Vembu, Balaji , Galoppo von Borries, Nicolas , Nurvitadhi, Eriko , Barik, Rajkishore , Lin, Tsung-Han , Ranganathan, Vasanth , Jahagirdar, Sanjeev , Shpeisman, Tatiana
IPC分类号： G06F7/544 , G06F7/483 , G06F9/30 , G06N3/04 , G06N3/063 , G06N3/08
摘要： The present disclosure provides a method, a data processing system and a graphics processing unit, GPU, comprising a memory controller; and a graphics multiprocessor coupled with the memory controller. The graphics multiprocessor includes a plurality of compute units configured to execute an instruction to perform a mixed-precision matrix operation on first input data and second input data; generate intermediate data based on a result of the mixed-precision matrix operation; convert the intermediate data to a floating-point format determined based on statistics associated with first output data; and output, as second output data, the converted intermediate data in the determined floating-point format.

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