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1. 发明授权

EP3028421B1 HIERARCHICAL/LOSSLESS PACKET PREEMPTION TO REDUCE LATENCY JITTER IN FLOW-CONTROLLED PACKET-BASED NETWORKS 有权
公开(公告)号：EP3028421B1
公开(公告)日：2020-02-26
申请号：EP14872243.2
申请日：2014-12-11
申请人： Intel Corporation
发明人： LOVETT, Thomas D. , CHENG, Albert S. , BIRRITTELLA, Mark S. , KUNZ, James A. , RIMMER, Todd M.
IPC分类号： H04L1/00 , H04L12/805 , H04L12/863 , H04L25/14 , H04L1/18 , H04L12/865

2. 发明公开

EP3078141A1 LANE ERROR DETECTION AND LANE REMOVAL MECHANISM TO REDUCE THE PROBABILITY OF DATA CORRUPTION 有权
标题翻译： SPURERKENNUNGS-及其微量元素距离机制来减少数据损坏的概率
公开(公告)号：EP3078141A1
公开(公告)日：2016-10-12
申请号：EP14867604.2
申请日：2014-12-05
申请人： Intel Corporation
发明人： BIRRITTELLA, Mark S.
IPC分类号： H04L1/00 , H04L1/20 , H04L29/10
CPC分类号： H04L1/0045 , H03M13/09 , H04L1/0058 , H04L1/0061 , H04L1/0071 , H04L1/08 , H04L1/1607 , H04L1/1657 , H04L1/1874
摘要： Method, apparatus, and systems for detecting lane errors and removing errant lanes in multi-lane links. Data comprising link packets is split into a plurality of bitstreams and transmitted over respective lanes of a multi-lane link in parallel. The bitstream data is received at multiple receive lanes of a receiver port and processed to reassemble link packets and to calculate a CRC over the data received on each lane. The link packets include a transmitted CRC that is compared to a received CRC to detect link packet errors. Upon detection of a link packet error, per-lane or per transfer group CRC values are stored, and a retry request is issued to retransmit the bad packet. In conjunction with receipt of the retransmitted packet, per-lane or per transfer group CRC values are recalculated over the received data and compared with the stored per-lane or per transfer group CRC values to detect the lane causing the link packet error.
摘要翻译：方法，设备和系统，用于检测车道的错误，并在多车道的左侧去除错误的车道。数据包括链路分组被分成位流的多个部分并加以反式mitted超过并联的多通道链路的respectivement车道。的位流数据在多个被接收接收的接收器端口的通道和处理，以重新组装链路包，并通过在每个车道接收到的数据来计算CRC。链路分组包括反式mitted CRC确实比较接收到的CRC检测链路数据包错误。一旦检测到链路分组错误的，每个车道或经由传送组CRC值被存储，并且重试请求发出重发错误的数据包。与接收到重传的分组的连词，每通道或经由传送组的CRC值被重新计算在所述接收到的数据，并与所存储的每个车道或经由传送组CRC值，以检测车道导致链路分组错误。

3. 发明公开

EP3028421A1 HIERARCHICAL/LOSSLESS PACKET PREEMPTION TO REDUCE LATENCY JITTER IN FLOW-CONTROLLED PACKET-BASED NETWORKS 有权
标题翻译： HIERARCHISCHE / VERLUSTLOSE PAKETBEVORRECHTIGUNG ZUR VERMINDERUNG VON LATENZJITTER在DURCHFLUSSGEREGELTEN PAKETNETZWERKEN
公开(公告)号：EP3028421A1
公开(公告)日：2016-06-08
申请号：EP14872243.2
申请日：2014-12-11
申请人： Intel Corporation
发明人： LOVETT, Thomas D. , CHENG, Albert S. , BIRRITTELLA, Mark S. , KUNZ, James A. , RIMMER, Todd M.
IPC分类号： H04L12/885
CPC分类号： H04L47/821 , H04L1/0041 , H04L1/0061 , H04L1/0071 , H04L1/12 , H04L1/1835 , H04L25/14 , H04L47/2441 , H04L47/365 , H04L47/621 , H04L47/6275
摘要： Methods, apparatus, and systems for implementing hierarchical and lossless packet preemption and interleaving to reduce latency jitter in flow-controller packet-based networks. Fabric packets are divided into a plurality of data units, with data units for different fabric packets buffered in separate buffers. Data units are pulled from the buffers and added to a transmit stream in which groups of data units are interleaved. Upon receipt by a receiver, the groups of data units are separated out and buffered in separate buffers under which data units for the same fabric packets are grouped together. In one aspect, each buffer is associated with a respective virtual lane (VL), and the fabric packets are effectively transferred over fabric links using virtual lanes. VLs may have different levels of priority under which data units for fabric packets in higher-priority VLs may preempt fabric packets in lower-priority VLs. By transferring data units rather than entire packets, transmission of a packet can be temporarily paused in favor of a higher-priority packet. Multiple levels of preemption and interleaving in a nested manner are supported.
摘要翻译：用于实现分级和无损分组抢占和交织以减少流控制器分组网络中的延迟抖动的方法，装置和系统。结构数据包被划分为多个数据单元，其中不同结构数据包的数据单元缓冲在单独的缓冲区中。从缓冲器中拉出数据单元并将其添加到数据单元组交错的发送流中。在由接收器接收时，数据单元组被分离出并且在单独的缓冲器中缓冲，在这些缓冲器中，相同结构数据包的数据单元被分组在一起。在一个方面，每个缓冲器与相应的虚拟通道（VL）相关联，并且使用虚拟通道在织物链路上有效地传送结构数据包。 VL可以具有不同的优先级，在该优先级下，较高优先级VL中的结构数据包的数据单元可以优先考虑低优先级VL中的结构分组。通过传送数据单元而不是整个分组，可以临时暂停分组的传输以有利于较高优先级的分组。支持以嵌套方式进行多级抢占和交织。

4. 发明公开

EP3208962A2 EFFICIENT LINK LAYER RETRY PROTOCOL UTILIZING IMPLICIT ACKNOWLEDGEMENTS 审中-公开
标题翻译：有效的链路层重试协议利用隐式认证
公开(公告)号：EP3208962A2
公开(公告)日：2017-08-23
申请号：EP17164293.7
申请日：2014-12-05
申请人： INTEL Corporation
发明人： BIRRITTELLA, Mark S.
IPC分类号： H04L1/18 , H04L29/10 , H04L1/16 , G06F9/00
CPC分类号： H04L1/1657 , G06F9/00 , H04L1/08 , H04L1/1867 , H04L1/1874 , H04L67/104
摘要： Methods, apparatus, and systems for implementing a link layer retry protocol utilizing implicit ACKnowledgements (ACKs). Peer link interfaces are configured to facilitate confirmed error-free delivery of link-layer packets through use of implicit ACKs, while also providing retransmission of packets for which errors are detected and guaranteeing the link control data is either successfully received or data transfer over the link is prevented. In conjunction with transmitting packets, reliable packets are copied into sequential slots in a replay buffer. Each link interface tracks the slot at which each reliable packet is buffered, and in response to detection of an error, a retry request is sent to the transmit-side to retransmit the errant packet. The previously buffered copy of the errant packet is retrieved from the replay buffer and retransmitted. Through use of a link roundtrip detection mechanism, absence of a retry request by the time a replay buffer has returned to the slot of a reliable packet (plus a predetermined number of additional transfer cycles, if applicable) provides an implicit ACK that the packet was received without error.
摘要翻译：用于利用隐式确认（ACK）来实现链路层重试协议的方法，设备和系统。对等链路接口被配置为通过使用隐式ACK来确认链路层分组的确认无差错传递，同时还提供检测到错误的分组的重传，并且保证链路控制数据被成功接收或者通过链路上的数据传输被阻止。结合发送分组，可靠分组被复制到重放缓冲区中的连续时隙中。每个链路接口跟踪缓冲每个可靠分组的时隙，并且响应于检测到错误，重发请求被发送到发送侧以重传错误分组。先前缓冲的错误数据包副本从重放缓冲区中检索并重新发送。通过使用链路往返检测机制，在重放缓冲区已经返回到可靠分组的时隙时（如果适用，加上预定数量的附加传输周期）时，不存在重试请求提供隐含的ACK，表明分组是无误地收到。

5. 发明公开

EP3078144A1 EFFICIENT LINK LAYER RETRY PROTOCOL UTILIZING IMPLICIT ACKNOWLEDGEMENTS 审中-公开
标题翻译： EFFIZIENTES VERBINDUNGSSCHICHTNEUVERSUCHSPROTOKOLL MITTELS IMPLIZITER QUITTIERUNGEN
公开(公告)号：EP3078144A1
公开(公告)日：2016-10-12
申请号：EP14866895.7
申请日：2014-12-05
申请人： Intel Corporation
发明人： BIRRITTELLA, Mark S.
IPC分类号： H04L1/18 , H04L29/10
CPC分类号： H04L1/1657 , G06F9/00 , H04L1/08 , H04L1/1867 , H04L1/1874 , H04L67/104
摘要： Methods, apparatus, and systems for implementing a link layer retry protocol utilizing implicit ACKnowledgements (ACKs). Peer link interfaces are configured to facilitate confirmed error-free delivery of link-layer packets through use of implicit ACKs, while also providing retransmission of packets for which errors are detected and guaranteeing the link control data is either successfully received or data transfer over the link is prevented. In conjunction with transmitting packets, reliable packets are copied into sequential slots in a replay buffer. Each link interface tracks the slot at which each reliable packet is buffered, and in response to detection of an error, a retry request is sent to the transmit-side to retransmit the errant packet. The previously buffered copy of the errant packet is retrieved from the replay buffer and retransmitted. Through use of a link roundtrip detection mechanism, absence of a retry request by the time a replay buffer has returned to the slot of a reliable packet (plus a predetermined number of additional transfer cycles, if applicable) provides an implicit ACK that the packet was received without error.
摘要翻译：用于实现使用隐式确认（ACK）的链路层重试协议的方法，装置和系统。对等链路接口被配置为通过使用隐式ACK来促进确认的无差错的链路层分组的传送，同时还提供重传检测到错误的分组，并且确保链路控制数据被成功接收或通过链路的数据传输被阻止结合发送分组，可靠的分组被复制到重放缓冲器中的顺序时隙中。每个链路接口跟踪缓冲每个可靠分组的时隙，并且响应于检测到错误，重发请求被发送到发送侧以重传错误分组。从重放缓冲区中检索先前缓存的错误数据包副本并重发。通过使用链路往返检测机制，在重播缓冲器已经返回到可靠分组的时隙（加上预定数量的附加传输周期（如果适用）的时候）没有重试请求提供了分组是收到没有错误。

6. 发明公开

EP3274857A1 MULTICHIP PACKAGE LINK 有权
标题翻译：多芯片封装链接
公开(公告)号：EP3274857A1
公开(公告)日：2018-01-31
申请号：EP16769240.9
申请日：2016-02-22
申请人： Intel Corporation
发明人： WAGH, Mahesh , WU, Zuoguo , IYER, Venkatraman , PASDAST, Gerald S. , BIRRITTELLA, Mark S. , AGARWAL, Ishwar , TEH, Lip Khoon , LIM, Su Wei , UPADHYAY, Anoop Kumar
IPC分类号： G06F13/42 , G06F13/14 , H04L12/701
CPC分类号： G06F13/4022 , G06F13/36 , G06F13/4068
摘要： A system-on-a-chip, such as a logical PHY, may be divided into hard IP blocks with fixed routing, and soft IP blocks with flexible routing. Each hard IP block may provide a fixed number of lanes. Using p hard IP blocks, where each block provides n data lanes, h=n*p total hard IP data lanes are provided. Where the system design calls for k total data lanes, it is possible that k≠h, so that ┌k/n┐ hard IP blocks provide h=n*p available hard IP data lanes. In that case, h−k lanes may be disabled. In cases where lane reversals occur, such as between hard IP and soft IP, bowtie routing may be avoided by the use of a multiplexer-like programmable switch within the soft IP.

7. 发明公开

EP3028411A1 LINK TRANSFER, BIT ERROR DETECTION AND LINK RETRY USING FLIT BUNDLES ASYNCHRONOUS TO LINK FABRIC PACKETS 有权
标题翻译：连接传输，以及相关的误码再次受审连接矩阵套餐异步熔接BUNDLE
公开(公告)号：EP3028411A1
公开(公告)日：2016-06-08
申请号：EP14866987.2
申请日：2014-12-05
申请人： Intel Corporation
发明人： BIRRITTELLA, Mark S.
IPC分类号： H04L12/70 , H04L1/00
CPC分类号： H04L47/36 , H04L49/30 , H04L69/22
摘要： Method, apparatus, and systems for Link Transfer, bit error detection and link retry using flit bundles asynchronous to link Fabric Packets. A first type of packet comprising a Fabric Packet is generated and its data content is divided into multiple data units called "flits." The flits are then bundled into a second type of packet comprising Link Transfer Packets (LTPs). The LTPs are then sent over single link segments in a fabric comprising many point-to-point links. Each LTP includes a CRC that is used to ensure that data transmitted over each link segment is error free, and comprises a unit of retransmission. The size of the fabric packets may vary, and they may be larger or smaller than an LTP. The transfer scheme enabled flits from multiple fabric packets to be bundled into a single LTP. Upon receipt at a fabric endpoint, the flits from the LTPs are extracted and reassembled to regenerate the Fabric Packets.

8. 发明公开

EP3018849A1 LINK LAYER SIGNAL SYNCHRONIZATION 审中-公开
标题翻译： VERBINDUNGSSCHICHTSIGNALSYNCHRONISIERUNG
公开(公告)号：EP3018849A1
公开(公告)日：2016-05-11
申请号：EP15190312.7
申请日：2015-10-16
申请人： Intel Corporation
发明人： BIRRITTELLA, Mark S.
IPC分类号： H04J3/06 , H04L7/00 , G06F5/06 , G06F1/12
CPC分类号： G06F1/12 , H04J3/0685 , H04J3/0697 , H04L7/0012 , H04L7/005
摘要： Embodiments of the present disclosure are directed toward signal synchronization in a link layer interconnect fabric. In one instance, an apparatus with logic for signal synchronization may include a clock synchronization logic to compare a core clock of the apparatus having a core clock frequency against a transmission clock of the apparatus having a first frequency or a reception clock of the apparatus having a second frequency, and, based on results of the comparison, generate a synchronized link transfer transmission clock or a synchronized link transfer reception clock respectively.. Other embodiments may be described and/or claimed.
摘要翻译：本公开的实施例涉及链路层互连结构中的信号同步。在一种情况下，具有用于信号同步的逻辑的装置可以包括时钟同步逻辑，用于将具有核心时钟频率的装置的核心时钟与具有第一频率的装置的传输时钟或装置的接收时钟进行比较第二频率，并且基于比较结果分别产生同步的链路传输传输时钟或同步的链路传送接收时钟。可以描述和/或要求保护其他实施例。

9. 发明公开

EP3846042A1 MULTICHIP PACKAGE LINK 审中-公开
公开(公告)号：EP3846042A1
公开(公告)日：2021-07-07
申请号：EP20206632.0
申请日：2016-02-22
申请人： INTEL Corporation
发明人： WAGH, Mahesh , WU, Zuoguo , IYER, Venkatraman , PASDAST, Gerald S. , BIRRITTELLA, Mark S. , AGARWAL, Ishwar , TEH, Lip Khoon , LIM, Su Wei , UPADHYAY, Anoop Kumar
IPC分类号： G06F13/42 , G06F13/14 , H04L12/701 , G06F13/36 , G06F13/40
摘要： The present disclosure provides an integrated circuit die. The integrated circuit die comprising a hard IP (HIP) subassembly comprising a plurality of hard logic blocks, a hard logic block associated with a plurality of data lanes. The plurality of data lanes having separate per-lane enables. The integrated circuit die comprising a plurality of protocol-specific logic blocks to communicate data in accordance with a corresponding plurality of data communication protocols. The plurality of protocol-specific logic blocks including a first protocol-specific logic block to communicate data in accordance with a first data communication protocol and a second protocol-specific logic block to communicate data in accordance with a second data communication protocol. The integrated circuit die comprising a soft IP (SIP) assembly having at least one soft logic block comprising routable logic to selectively map a data lane of the plurality of data lanes to the first protocol-specific logic block and a data lane of the plurality of data lanes to the second protocol-specific logic block.

10. 发明公开

EP3796181A1 MULTICHIP PACKAGE LINK 审中-公开
公开(公告)号：EP3796181A1
公开(公告)日：2021-03-24
申请号：EP20206623.9
申请日：2016-02-22
申请人： INTEL Corporation
发明人： WAGH, Mahesh , WU, Zuoguo , IYER, Venkatraman , PASDAST, Gerald S. , BIRRITTELLA, Mark S. , AGARWAL, Ishwar , TEH, Lip Khoon , LIM, Su Wei , UPADHYAY, Anoop Kumar
IPC分类号： G06F13/42 , G06F13/14 , H04L12/701 , G06F13/36 , G06F13/40
摘要： The present disclosure provides a multi-chip package comprising a substrate, a first integrated circuit (IC) die packaged onto the substrate and a second IC die packaged onto the substrate and connected to the first IC die using a multi-chip package link (MCPL). The MCPL including an upstream channel and a downstream channel each associated with a set of lanes. The first IC die comprising a CPU and an interface to connect the CPU. The interface including a physical layer (PHY) to provide a physical connection over which data is communicated between the first IC die and the second IC die. The PHY comprising a transmitter to transmit data to the second IC die, a receiver to receive data from the second IC die and a clock recovery circuit to center a clock signal in both the time domain and the voltage domain and to receive a clock signal from the second IC die over a strobe lane. To center in the time domain, the clock recovery circuit is to determine a phase of the clock signal and to adjust the phase of the clock signal. To center in the voltage domain, the clock recovery circuit is to adjust a reference voltage. The clock recovery circuit to sample data signals in accordance with the reference voltage and the clock signal using a plurality of data samplers for each lane.

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