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    • 5. 发明公开
    • Stacked chip device
    • Chipstapelvorrichtung
    • EP2903158A2
    • 2015-08-05
    • EP15152490.7
    • 2015-01-26
    • Innochips Technology Co., Ltd.
    • Park, In KilNoh, Tae HyungKim, Gyeong TaeSeo, Tae GeunLee, Myung HoLee, Min Soo
    • H03H7/01H03H1/00
    • H03H7/0115H03H2001/0085
    • The present disclosure relates to a stacked chip device (11) including a first stack unit (B) comprising a plurality of electrode patterns (111, 112) respectively disposed for a unit device region and common electrode patterns (121) formed to be connected to overlap the unit device regions, a second stack unit (A) disposed on a top portion of the first stack unit (B) and comprising a plurality of first conductor patterns (211-216), and a third stack unit (C) disposed on a bottom portion of the first stack unit (B) and comprising a plurality of second conductor patterns (311-316), wherein the first and second conductor patterns (211-216; 311-316) are formed on a plurality of sheets (201-206; 301-306), the first and second conductor patterns formed on one sheet are formed across a plurality of unit device regions, and the first and second conductor patterns (211-216; 311-316) are connected vertically through vias (511, 512, 521, 522) formed penetrating through at least some of the sheets.
    • 本公开涉及一种堆叠式芯片装置(11),包括:第一堆叠单元(B),包括分别设置用于单位装置区域的多个电极图案(111,112)和形成为连接到 与所述单元设备区域重叠;第二堆叠单元(A),设置在所述第一堆叠单元(B)的顶部并且包括多个第一导体图案(211-216);以及第三堆叠单元(C) 第一堆叠单元(B)的底部并且包括多个第二导体图案(311-316),其中第一和第二导体图案(211-216; 311-316)形成在多个片材(201 -206; 301-306),形成在一个片材上的第一和第二导体图案横跨多个单元器件区域形成,并且第一和第二导体图案(211-216; 311-316)通过通孔垂直连接 511,512,521,522)穿透至少一些片材 。
    • 8. 发明公开
    • Stacked chip device
    • 堆叠芯片设备
    • EP2903158A3
    • 2015-11-18
    • EP15152490.7
    • 2015-01-26
    • Innochips Technology Co., Ltd.
    • Park, In KilNoh, Tae HyungKim, Gyeong TaeSeo, Tae GeunLee, Myung HoLee, Min Soo
    • H03H7/01H03H1/00
    • H03H7/0115H03H2001/0085
    • The present disclosure relates to a stacked chip device (11) including a first stack unit (B) comprising a plurality of electrode patterns (111, 112) respectively disposed for a unit device region and common electrode patterns (121) formed to be connected to overlap the unit device regions, a second stack unit (A) disposed on a top portion of the first stack unit (B) and comprising a plurality of first conductor patterns (211-216), and a third stack unit (C) disposed on a bottom portion of the first stack unit (B) and comprising a plurality of second conductor patterns (311-316), wherein the first and second conductor patterns (211-216; 311-316) are formed on a plurality of sheets (201-206; 301-306), the first and second conductor patterns formed on one sheet are formed across a plurality of unit device regions, and the first and second conductor patterns (211-216; 311-316) are connected vertically through vias (511, 512, 521, 522) formed penetrating through at least some of the sheets.
    • 本发明涉及一种堆叠芯片器件(11),其包括:第一堆叠单元(B),其包括分别设置用于单元器件区域的多个电极图案(111,112);以及公共电极图案(121),其形成为连接到 (B)的顶部上并且包括多个第一导体图案(211-216)的第二堆叠单元(A)以及设置在第一堆叠单元(B)上的第三堆叠单元(C) (B)的底部并且包括多个第二导体图案(311-316),其中第一和第二导体图案(211-216; 311-316)形成在多个片材(201 -206,301-306),形成在一个薄片上的第一和第二导体图案横跨多个单元器件区域形成,并且第一和第二导体图案(211-216; 311-316)通过通孔垂直连接( 穿过至少一些片材形成 。