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1. 发明公开

EP3226142A1 HANDLING MEMORY REQUESTS 有权
标题翻译：处理内存请求
公开(公告)号：EP3226142A1
公开(公告)日：2017-10-04
申请号：EP17163527.9
申请日：2017-03-29
申请人： Imagination Technologies Limited
发明人： LANDERS, Mark , ROBINSON, Martin John
IPC分类号： G06F12/0897 , G06F12/1027 , G06F12/1045 , G06F12/0891 , G06F12/02 , G06F13/16
CPC分类号： G06F9/467 , G06F9/45558 , G06F12/0811 , G06F12/0831 , G06F12/0891 , G06F12/0897 , G06F12/1027 , G06F12/1063 , G06F13/1605 , G06F2009/45583 , G06F2212/1008 , G06F2212/1024 , G06F2212/60 , G06F2212/621 , G06F2212/684
摘要： A converter module is described which handles memory requests issued by a cache (e.g. an on-chip cache), where these memory requests include memory addresses defined within a virtual memory space. The converter module receives these requests, issues each request with a transaction identifier and uses that identifier to track the status of the memory request. The converter module sends requests for address translation to a memory management unit and where there the translation is not available in the memory management unit receives further memory requests from the memory management unit. The memory requests are issued to a memory via a bus and the transaction identifier for a request is freed once the response has been received from the memory. When issuing memory requests onto the bus, memory requests received from the memory management unit may be prioritized over those received from the cache.
摘要翻译：描述处理由高速缓存（例如，片上高速缓存）发出的存储器请求的转换器模块，其中这些存储器请求包括在虚拟存储器空间内定义的存储器地址。转换器模块接收这些请求，用事务标识符发出每个请求，并使用该标识符来跟踪内存请求的状态。转换器模块向存储器管理单元发送地址转换请求，并且在存储器管理单元接收来自存储器管理单元的进一步的存储器请求的情况下，转换不可用。存储器请求通过总线发送到存储器，并且一旦从存储器接收到响应，就释放用于请求的事务标识符。当向总线发出存储器请求时，从存储器管理单元接收到的存储器请求可以优先于从高速缓存器接收的存储器请求。

2. 发明授权

EP3447647B1 HANDLING MEMORY REQUESTS 有权
公开(公告)号：EP3447647B1
公开(公告)日：2020-03-25
申请号：EP18192615.5
申请日：2017-03-29
申请人： Imagination Technologies Limited
发明人： LANDERS, Mark , ROBINSON, Martin John
IPC分类号： G06F12/0897 , G06F12/1027 , G06F12/1045 , G06F12/0891 , G06F12/02 , G06F13/16 , G06F12/0811 , G06F12/0831 , G06F9/455 , G06F9/46

3. 发明公开

EP3534269A1 MEMORY INTERFACE 有权转让
公开(公告)号：EP3534269A1
公开(公告)日：2019-09-04
申请号：EP19159832.5
申请日：2019-02-27
申请人： Imagination Technologies Limited
发明人： ROBINSON, Martin John , LANDERS, Mark
IPC分类号： G06F12/0831 , G06F12/1018
摘要： A memory interface for interfacing between a memory bus addressable using a physical address space and a cache memory addressable using a virtual address space, the memory interface comprising: a memory management unit configured to maintain a mapping from the virtual address space to the physical address space; and a coherency manager comprising a reverse translation module configured to maintain a mapping from the physical address space to the virtual address space; wherein the memory interface is configured to: receive a memory read request from the cache memory, the memory read request being addressed in the virtual address space; translate the memory read request, at the memory management unit, to a translated memory read request addressed in the physical address space for transmission on the memory bus; receive a snoop request from the memory bus, the snoop request being addressed in the physical address space; and translate the snoop request, at the coherency manager, to a translated snoop request addressed in the virtual address space for processing in connection with the cache memory.

4. 发明授权

EP3226142B1 HANDLING MEMORY REQUESTS 有权
公开(公告)号：EP3226142B1
公开(公告)日：2019-03-06
申请号：EP17163527.9
申请日：2017-03-29
申请人： Imagination Technologies Limited
发明人： LANDERS, Mark , ROBINSON, Martin John
IPC分类号： G06F12/0897 , G06F12/1027 , G06F12/1045 , G06F12/0891 , G06F12/02 , G06F13/16 , G06F12/0811 , G06F12/0831 , G06F9/455 , G06F9/46

5. 发明公开

EP3534268A1 MEMORY INTERFACE 有权
公开(公告)号：EP3534268A1
公开(公告)日：2019-09-04
申请号：EP19159831.7
申请日：2019-02-27
申请人： Imagination Technologies Limited
发明人： ROBINSON, Martin John , LANDERS, Mark
IPC分类号： G06F12/0831 , G06F12/0846 , G06F12/1018
摘要： A memory interface for interfacing between a memory bus and a cache memory, comprising: a plurality of bus interfaces configured to transfer data between the memory bus and the cache memory; and a plurality of snoop processors configured to receive snoop requests from the memory bus; wherein each snoop processor is associated with a respective bus interface and each snoop processor is configured, on receiving a snoop request, to determine whether the snoop request relates to the bus interface associated with that snoop processor and to process the snoop request in dependence on that determination.

6. 发明公开

EP3534267A1 COHERENCY MANAGER 有权
公开(公告)号：EP3534267A1
公开(公告)日：2019-09-04
申请号：EP19159829.1
申请日：2019-02-27
申请人： Imagination Technologies Limited
发明人： ROBINSON, Martin John , LANDERS, Mark
IPC分类号： G06F12/0831 , G06F12/1018 , G06F12/1045
摘要： A coherency manager for receiving snoop requests addressed in a physical address space, the snoop requests relating to a cache memory addressable using a virtual address space, the cache memory having a plurality of coherent cachelines, the coherency manager comprising: a reverse translation module configured to maintain a mapping from physical addresses to virtual addresses for each coherent cacheline held in the cache memory; and a snoop processor configured to: receive a snoop request relating to a physical address; in response to the received snoop request, determine whether the physical address is mapped to a virtual address in the reverse translation module; and process the snoop request in dependence on that determination.

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