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1. 发明公开

EP2605273A3 Method for forming isolation trenches in micro-bump interconnect structures and devices obtained thereof 审中-公开
标题翻译：在微凸点互连结构中形成隔离沟槽的方法和由此获得的器件
公开(公告)号：EP2605273A3
公开(公告)日：2017-08-09
申请号：EP12197098.2
申请日：2012-12-13
申请人： IMEC , Katholieke Universiteit Leuven K.U. Leuven R&D
发明人： Zhang, Wenqi , Wang, Wei-E , Eneman, Geert , Beyne, Eric , Ivankovic, Andrej
IPC分类号： H01L23/31 , H01L23/48 , H01L25/065
CPC分类号： H01L21/4853 , H01L21/185 , H01L23/3178 , H01L23/481 , H01L23/49827 , H01L23/5384 , H01L24/03 , H01L24/05 , H01L24/06 , H01L24/13 , H01L24/14 , H01L25/0657 , H01L2224/02235 , H01L2224/0401 , H01L2224/05009 , H01L2224/05546 , H01L2224/05562 , H01L2224/0557 , H01L2224/05573 , H01L2224/05647 , H01L2224/13023 , H01L2224/13025 , H01L2224/13111 , H01L2224/14181 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2225/06565 , H01L2924/00014 , H01L2924/01029 , H01L2924/01322 , H01L2924/00 , H01L2224/05552
摘要： The invention is related to a substrate (100) suitable for use in a stack of interconnected substrates, comprising :
- A base layer (130), having a front side (135) and a back side (115) surface parallel to the plane of the base layer,
- One or more interconnect structures, each of said structures comprising :
● A via (110) filled with an electrically conductive material, said via running through the complete thickness of the base layer, thereby forming an electrical connection between said front side and back side surfaces of the base layer,
● on the back side surface (115) of the base layer : a landing pad (160) and a microbump (165) in electrical connection with said filled via,

characterized in that the backside surface (115) of said base layer (130) comprises one or more isolation ring trenches (145), each of said trenches surrounding one or more of said interconnect structures. The invention is equally related to a stack of said substrates, and to methods for producing said substrates and said stack of substrates.
摘要翻译：本发明涉及一种适用于一叠互连基板的基板（100），包括： - 基层（130），其具有平行于所述平面的前侧（135）和后侧（115） - 一个或多个互连结构，每个所述结构包括：●填充有导电材料的通孔（110），所述通孔延伸穿过基层的整个厚度，由此在所述前端在所述基层的后侧表面（115）上：接合垫（160）和与所述填充通孔电连接的微凸块（165），其特征在于，所述后侧表面所述基层（130）的所述沟槽（115）包括一个或多个隔离环沟槽（145），每个所述沟槽围绕一个或多个所述互连结构。本发明同样涉及所述衬底的堆叠，以及用于制造所述衬底和所述衬底的堆叠的方法。

2. 发明公开

EP2605273A2 Method for forming isolation trenches in micro-bump interconnect structures and devices obtained thereof 审中-公开
标题翻译：一种用于制造绝缘沟槽的在微凸块接合的结构和设备由此产生过程
公开(公告)号：EP2605273A2
公开(公告)日：2013-06-19
申请号：EP12197098.2
申请日：2012-12-13
申请人： IMEC , Katholieke Universiteit Leuven K.U. Leuven R&D
发明人： Zhang, Wenqi , Wang, Wei-E , Eneman, Geert , Beyne, Eric , Ivankovic, Andrej
IPC分类号： H01L23/31 , H01L23/48 , H01L25/065
CPC分类号： H01L21/4853 , H01L21/185 , H01L23/3178 , H01L23/481 , H01L23/49827 , H01L23/5384 , H01L24/03 , H01L24/05 , H01L24/06 , H01L24/13 , H01L24/14 , H01L25/0657 , H01L2224/02235 , H01L2224/0401 , H01L2224/05009 , H01L2224/05546 , H01L2224/05562 , H01L2224/0557 , H01L2224/05573 , H01L2224/05647 , H01L2224/13023 , H01L2224/13025 , H01L2224/13111 , H01L2224/14181 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2225/06565 , H01L2924/00014 , H01L2924/01029 , H01L2924/01322 , H01L2924/00 , H01L2224/05552
摘要： The invention is related to a substrate (100) suitable for use in a stack of interconnected substrates, comprising :
- A base layer (130), having a front side (135) and a back side (115) surface parallel to the plane of the base layer,
- One or more interconnect structures, each of said structures comprising :
● A via (110) filled with an electrically conductive material, said via running through the complete thickness of the base layer, thereby forming an electrical connection between said front side and back side surfaces of the base layer,
● on the back side surface (115) of the base layer : a landing pad (160) and a microbump (165) in electrical connection with said filled via,

characterized in that the backside surface (115) of said base layer (130) comprises one or more isolation ring trenches (145), each of said trenches surrounding one or more of said interconnect structures. The invention is equally related to a stack of said substrates, and to methods for producing said substrates and said stack of substrates.
摘要翻译：本发明涉及一种基片（100），适用于相互连接的基片的叠层，包括： - 具有前侧（135）和背面的基体层（130）（115）面平行于该平面基础层， - 一个或多个互连结构，每个所述结构包括： - 经由在导电材料填充（110），所述经由穿过基极层的整个厚度上运行，从而形成在所述的电连接基础层的正面和背面的表面， - 所述基础层的所述背侧表面（115）上：在DASS特点连接焊盘（160）和在填充通孔，与所述电连接的微凸块（165）管芯所述基层（130）的背侧表面（115）包括一个或多个隔离沟槽环（145），每个周围的一个或多个所述互连结构的所述沟槽中的。本发明同样涉及到所述衬底的堆叠，以及用于产生所述基片和基片的所述叠层的方法。

3. 发明授权

EP2701189B1 Substrate, fabrication method of such a substrate, method of self-assembly of such substrates and device obtained thereof 有权
标题翻译：基板，其制造方法中，用于这种衬底的自组装方法和由此生产设备
公开(公告)号：EP2701189B1
公开(公告)日：2016-01-20
申请号：EP12181742.3
申请日：2012-08-24
申请人： IMEC
发明人： Soussan, Philippe , Zhang, Wenqi , Armini, Silvia
IPC分类号： H01L21/98 , H01L21/60 , H01L23/485 , H01L25/065
CPC分类号： H01L24/11 , H01L24/13 , H01L24/14 , H01L24/16 , H01L24/81 , H01L25/50 , H01L2224/0361 , H01L2224/03912 , H01L2224/0401 , H01L2224/05572 , H01L2224/05611 , H01L2224/05624 , H01L2224/05647 , H01L2224/05666 , H01L2224/05681 , H01L2224/10135 , H01L2224/11462 , H01L2224/11912 , H01L2224/1308 , H01L2224/13082 , H01L2224/13083 , H01L2224/13109 , H01L2224/13111 , H01L2224/13147 , H01L2224/81002 , H01L2224/81007 , H01L2224/81143 , H01L2224/81193 , H01L2224/81815 , H01L2225/06513 , H01L2225/06593 , H01L2924/00014 , H01L2924/12042 , H01L2924/1461 , H01L2924/014 , H01L2924/00 , H01L2224/05552
摘要： A method of defining regions with different surface liquid tension properties on a substrate (101) is disclosed, said method comprising providing a substrate with a main surface having a first surface liquid tension property, the main surface being at least partially covered with a seed layer (103) and further comprising at least one micro-bump (105) formed on the seed layer, thereby leaving part of the seed layer exposed, patterning the exposed seed layer thereby exposing part of the main surface for forming at least one closed loop structure enclosing a region of the main surface; and chemically treating the main surface of the wafer thereby generating on the surface of at least one closed loop structure and at least one micro- bump a second surface liquid tension property, the second surface liquid tension property being substantially different from the first surface liquid tension property of the main surface.

4. 发明公开

EP2819162A1 Method for producing contact areas on a semiconductor substrate 审中-公开
标题翻译：西班牙语VERA Kontaktbereichen auf einem Halbleitersubstrat
公开(公告)号：EP2819162A1
公开(公告)日：2014-12-31
申请号：EP13173335.4
申请日：2013-06-24
申请人： IMEC
发明人： Beyne, Eric , Zhang, Wenqi , Jamieson, Jeraldine , Swinnen, Bart
IPC分类号： H01L23/498 , H01L21/48
CPC分类号： H01L24/06 , H01J2237/334 , H01J2237/3342 , H01J2237/3347 , H01J2237/3348 , H01J2237/338 , H01J2237/3382 , H01L21/4853 , H01L23/49811 , H01L24/03 , H01L2224/03466 , H01L2224/0401 , H01L2224/0601 , H01L2224/16237
摘要： The present invention is related to a method for producing hollow contact areas suitable for insertion bonding, formed on a semiconductor substrate (1) comprising a stack of one or more metallization layers on its surface. Openings are etched in a dielectric layer by plasma etching, using a resist layer as a mask. The resist material and the plasma etch parameters are chosen so as to obtain openings with sloped sidewalls that have a predefined slope, due to the controlled formation of a polymer layer forming on the sidewalls of the resist hole and the hollow contact opening formed during the etch step. According to a preferred embodiment, metal deposited in the hollow contact areas and on top of the dielectric is planarized using Chemical Mechanical Polishing, leading to mutually isolated contact areas. An array of such areas can be produced having smaller pitch compared to prior art arrays. The invention is equally related to components obtainable by the method of the invention, and to a package comprising such components.
摘要翻译：本发明涉及一种用于制造适于插入接合的中空接触区域的方法，该方法形成在其表面上包括一个或多个金属化层的叠层的半导体衬底（1）上。使用抗蚀剂层作为掩模，通过等离子体蚀刻在电介质层中蚀刻开口。选择抗蚀剂材料和等离子体蚀刻参数，以便获得具有预定斜率的具有倾斜侧壁的开口，这是由于形成在抗蚀剂孔的侧壁上形成的聚合物层和在蚀刻期间形成的中空接触开口步。根据优选实施例，沉积在中空接触区域中并且在电介质顶部上的金属使用化学机械抛光进行平面化，导致相互隔离的接触区域。与现有技术的阵列相比，可以产生具有较小间距的这种区域的阵列。本发明与通过本发明的方法可获得的组分以及包含这些组分的包装同样相关。

5. 发明公开

EP2701189A1 Method for self-assembly of substrates and devices obtained thereof 有权
标题翻译：基板，其制造方法中，用于这种衬底的自组装方法和由此生产设备
公开(公告)号：EP2701189A1
公开(公告)日：2014-02-26
申请号：EP12181742.3
申请日：2012-08-24
申请人： IMEC
发明人： Soussan, Philippe , Zhang, Wenqi , Armini, Silvia
IPC分类号： H01L21/98 , H01L21/60 , H01L23/485 , H01L25/065
CPC分类号： H01L24/11 , H01L24/13 , H01L24/14 , H01L24/16 , H01L24/81 , H01L25/50 , H01L2224/0361 , H01L2224/03912 , H01L2224/0401 , H01L2224/05572 , H01L2224/05611 , H01L2224/05624 , H01L2224/05647 , H01L2224/05666 , H01L2224/05681 , H01L2224/10135 , H01L2224/11462 , H01L2224/11912 , H01L2224/1308 , H01L2224/13082 , H01L2224/13083 , H01L2224/13109 , H01L2224/13111 , H01L2224/13147 , H01L2224/81002 , H01L2224/81007 , H01L2224/81143 , H01L2224/81193 , H01L2224/81815 , H01L2225/06513 , H01L2225/06593 , H01L2924/00014 , H01L2924/12042 , H01L2924/1461 , H01L2924/014 , H01L2924/00 , H01L2224/05552
摘要： A method of defining regions with different surface liquid tension properties on a substrate (101) is disclosed, said method comprising providing a substrate with a main surface having a first surface liquid tension property, the main surface being at least partially covered with a seed layer (103) and further comprising at least one micro-bump (105) formed on the seed layer, thereby leaving part of the seed layer exposed, patterning the exposed seed layer thereby exposing part of the main surface for forming at least one closed loop structure enclosing a region of the main surface; and chemically treating the main surface of the wafer thereby generating on the surface of at least one closed loop structure and at least one micro- bump a second surface liquid tension property, the second surface liquid tension property being substantially different from the first surface liquid tension property of the main surface.
摘要翻译：的方法的定义上的基片具有不同表面液体张力特性的区域（101）是圆盘游离缺失，所述方法包括提供一个基片具有第一表面液体张力性质的主表面，所述主表面至少部分地覆盖有籽晶层（103）和还包括形成在晶种层上，从而留下露出的种子层的一部分，图案化暴露的种子层，从而暴露所述主表面的一部分上形成至少一个闭环结构的至少一个微凸块（105）包围的主表面的区域; 和化学处理的晶片，由此产生至少一个闭环结构的表面上和至少一个凸点微的第二表面张力液体性能的主要表面，所述第二表面张力液体属性与所述第一表面张力液体基本上不同主表面的属性。

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