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1. 发明公开

EP4385944A1 A METHOD FOR BONDING AND INTERCONNECTING MICRO-ELECTRONIC COMPONENTS 审中-公开
公开(公告)号：EP4385944A1
公开(公告)日：2024-06-19
申请号：EP22213368.8
申请日：2022-12-14
申请人： Imec VZW
发明人： Derakhshandeh, Jaber , Beyne, Eric
IPC分类号： B81B7/00 , B81C1/00 , B81C3/00 , H01L23/00
CPC分类号： H10N69/00 , H01L24/80 , H01L2224/8089520130101 , H01L2224/8089620130101 , H01L2224/0814520130101 , H01L24/08 , H01L2224/0805820130101 , H01L2224/0805320130101 , H01L2224/8036520130101 , B81C1/00095 , B81C2203/03620130101 , B81C1/00269 , B81C2203/03520130101
摘要： A first and second substrate (24,25) are bonded to each other to form a 3D assembly of micro-electronic components. Both substrates comprise a plurality of first cavities (17) open to the respective bonding surfaces (30) and at least one substrate comprises a second cavity (10) that is larger than the first cavities in terms of its in-plane dimensions, and possibly also in terms of its depth. Prior to bonding, an electrically conductive layer (16) is produced conformally on each substrate. Said layer is patterned in the large cavity or cavities (10) and in said large cavity or cavities a micro-electronic device or a portion thereof (11) is fabricated. Thereafter, the bonding surfaces are planarized, removing the conformal layer (16) from said bonding surfaces (30), after which the substrates are bonded to form the assembly, wherein the first cavities of both substrates are brought into mutual contact to form an electrical connection. Possibly, the first cavities (17) may be filled with a contact material (33) prior to the planarization step. Any device in the large cavities may be contacted through suitable connection means such as TSV connections (4,5) or back end of line interconnect levels.

2. 发明公开

EP4187600A1 A SEMICONDUCTOR COMPONENT COMPRISING BACK SIDE I/O SIGNAL ROUTING 审中-实审
公开(公告)号：EP4187600A1
公开(公告)日：2023-05-31
申请号：EP21210849.2
申请日：2021-11-26
申请人： Imec VZW
发明人： Chen, Shih-Hung , Beyne, Eric , Van der Plas, Geert
IPC分类号： H01L27/02 , H01L21/768 , H01L23/522 , H01L23/528
摘要： The invention is related to a semiconductor component, for example an integrated circuit chip, comprising a semiconductor substrate (1) having active devices (7) at the front side thereof and I/O terminals (19) at the back side of the component. The terminals are connected to the active devices through TSV connections (16b) and buried rails (15b) in an area (5) of the substrate that is separate from the area (4) in which the active devices are located. According to the invention, the I/O TSV connections (16b) are located in a floating well (25) of the substrate that is separated from the rest of the substrate by a second well (26) formed of material of the opposite conductivity type compared to the material of the floating well. The second well (26) comprises at least one contact (28) configured to be coupled to a voltage that is suitable for reverse-biasing the junction (27) between the floating well (25) and the second well (26). In this way, a small capacitance is placed in series with the large parasitic capacitance generated by a thin dielectric liner that isolates the I/O TSVs and I/O rails from the substrate, thereby mitigating the negative effect of the large parasitic capacitance. According to preferred embodiments, additional contacts and conductors are provided which are configured to create an ESD protection circuit for protecting the I/O TSVs (16b) and the I/O rails (15b) from electrostatic discharges.

3. 发明授权

EP3185026B1 PROBING DEVICE FOR TESTING INTEGRATED CIRCUITS 有权
公开(公告)号：EP3185026B1
公开(公告)日：2020-10-28
申请号：EP15202281.0
申请日：2015-12-23
申请人： IMEC VZW
发明人： Wang, Teng , Marinissen, Erik Jan , Beyne, Eric
IPC分类号： G01R31/28 , G01R1/073

4. 发明授权

EP3324436B1 AN INTEGRATED CIRCUIT CHIP WITH POWER DELIVERY NETWORK ON THE BACKSIDE OF THE CHIP 有权
公开(公告)号：EP3324436B1
公开(公告)日：2020-08-05
申请号：EP17196921.5
申请日：2017-10-17
申请人： IMEC vzw
发明人： Beyne, Eric , Ryckaert, Julien
IPC分类号： H01L23/528 , H01L23/535 , H01L23/48 , H01L21/768 , H01L21/762 , H01L21/8238 , H01L27/092

5. 发明授权

EP2408006B1 Method for forming 3D-interconnect structures with airgaps and corresponding device 有权转让
公开(公告)号：EP2408006B1
公开(公告)日：2019-07-03
申请号：EP11174114.6
申请日：2011-07-15
申请人： IMEC VZW
发明人： Sabuncuoglu Tezcan, Deniz , Civale, Yann , Beyne, Eric
IPC分类号： H01L21/768 , H01L23/48

6. 发明公开

EP3324436A1 AN INTEGRATED CIRCUIT CHIP WITH POWER DELIVERY NETWORK ON THE BACKSIDE OF THE CHIP 有权
公开(公告)号：EP3324436A1
公开(公告)日：2018-05-23
申请号：EP17196921.5
申请日：2017-10-17
申请人： IMEC vzw
发明人： Beyne, Eric , Ryckaert, Julien
IPC分类号： H01L23/528 , H01L21/768 , H01L23/48 , H01L23/535
摘要： In an IC according to the invention, power and ground rails are incorporated in the front end of line (FEOL). These power and ground rails are at the same level as the active devices and are therefore buried deep in the IC, as seen from the front of the chip. The connection from the buried interconnects to the source and drain areas is established by so-called 'local interconnects'. These local interconnects are not part of the back end of line, but they are for the most part embedded in a pre-metal dielectric layer onto which the BEOL is produced. Further according to the invention, the power delivery network of the IC is located in its entirety on the backside of the chip. The PDN is connected to the buried interconnects through suitable connections, for example metal-filled vias of the type known as 'through-semiconductor vias' or 'through silicon vias' (TSV). The invention is equally related to methods for producing an IC according to the invention.

8. 发明公开

EP2408006A2 Method for forming 3D-interconnect structures with airgaps 有权转让
标题翻译： Verfahren zur Herstellung von 3D-Interconnectstrukturen mit Luftspalten
公开(公告)号：EP2408006A2
公开(公告)日：2012-01-18
申请号：EP11174114.6
申请日：2011-07-15
申请人： IMEC
发明人： Sabuncuoglu Tezcan, Deniz , Civale, Yann , Beyne, Eric
IPC分类号： H01L21/768 , H01L23/48
CPC分类号： H01L21/76898 , H01L21/7682 , H01L23/481 , H01L2224/0401 , H01L2224/05 , H01L2224/13025 , H01L2224/131 , H01L2924/12044 , H01L2924/1461 , H01L2924/014 , H01L2924/00
摘要： Ultra-low capacitance interconnect structures, preferably Through Silicon Via interconnects and methods for fabricating said interconnects are disclosed. The fabrication method comprises the steps of providing a substrate (1) having a first main surface (S1), producing at least one hollow trench-like structure (R1) therein from the first main surface (S1), said trench-like structure surrounding an inner pillar structure (22) of substrate material, depositing a dielectric liner (24) which pinches off said hollow trench-like structure (R1) at the first main surface (S1) such that an airgap is created in the center of hollow trench-like structure (R1) and further creating a TSV hole (23) and filling it at least partly with conductive material.
摘要翻译：公开了超低电容互连结构，优选通过硅通孔互连和用于制造所述互连的方法。该制造方法包括以下步骤：提供具有第一主表面（S1）的基板（1），从第一主表面（S1）至少形成一个中空沟槽状结构（R1），所述沟槽状结构围绕衬底材料的内柱结构（22），沉积在第一主表面（S1）处夹住所述中空沟槽状结构（R1）的电介质衬垫（24），使得在中空沟槽的中心产生气隙（R1），并且进一步产生TSV孔（23）并且至少部分地用导电材料填充TSV孔。

9. 发明公开

EP2339627A1 Window interposed die packaging 审中-公开
标题翻译： Chipverkapselung mit Fenster-Zwischenstück
公开(公告)号：EP2339627A1
公开(公告)日：2011-06-29
申请号：EP09180763.6
申请日：2009-12-24
申请人： IMEC
发明人： Beyne, Eric , Limaye, Paresh
IPC分类号： H01L23/538 , H01L25/065
CPC分类号： H01L23/5389 , H01L21/568 , H01L23/3128 , H01L23/36 , H01L23/562 , H01L24/97 , H01L25/0657 , H01L2224/16145 , H01L2224/16225 , H01L2224/16227 , H01L2224/73204 , H01L2224/73253 , H01L2224/81005 , H01L2224/83005 , H01L2224/94 , H01L2224/97 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01016 , H01L2924/01023 , H01L2924/01029 , H01L2924/01032 , H01L2924/01033 , H01L2924/01075 , H01L2924/014 , H01L2924/07811 , H01L2924/09701 , H01L2924/12042 , H01L2924/14 , H01L2924/15311 , H01L2924/15787 , H01L2924/15788 , H01L2924/181 , H01L2924/18161 , H01L2924/351 , H01L2924/00 , H01L2224/81 , H01L2224/83
摘要： A semiconductor device is described advantageously making use of the interposer principle. The semiconductor device comprises at least one semiconductor die (130), a window substrate (110) being an inorganic substrate comprising at least one window-shaped cavity (120) for mounting the at least one semiconductor die (130), the window substrate (110) having interconnect structures (140). Furthermore, the at least one semiconductor die is positioned inside the at least one cavity and is connected to the interconnect structures, providing connections to another level of assembly or packaging of the semiconductor device (100). The invention also relates to a method of manufacturing such a semiconductor device.
摘要翻译：利用插入器原理有利地描述了半导体器件。所述半导体器件包括至少一个半导体管芯（130），窗口衬底（110），其是无机衬底，所述无机衬底包括至少一个用于安装所述至少一个半导体管芯（130）的窗形空腔（120），所述窗口衬底 110）具有互连结构（140）。此外，至少一个半导体管芯位于至少一个空腔的内部，并连接到互连结构，提供与半导体器件（100）的另一组装或封装的连接。本发明还涉及一种制造这种半导体器件的方法。

10. 发明公开

EP2075834A1 Solder bumps for flip chip bonding with higher density 审中-公开
标题翻译： Löthöckerzum Flip-Chip-Bonden mitHöhererDichte
公开(公告)号：EP2075834A1
公开(公告)日：2009-07-01
申请号：EP08150793.1
申请日：2008-01-29
申请人： INTERUNIVERSITAIR MICROELEKTRONICA CENTRUM vzw (IMEC) , Katholieke Universiteit Leuven, K.U. Leuven R&D
发明人： Limaye, Paresh , Labie, Riet , Beyne, Eric , Soussan, Philippe , De Moor, Piet
IPC分类号： H01L23/485
CPC分类号： H01L24/11 , H01L24/03 , H01L24/05 , H01L24/12 , H01L24/16 , H01L24/81 , H01L2224/02166 , H01L2224/0401 , H01L2224/05568 , H01L2224/0558 , H01L2224/05599 , H01L2224/05639 , H01L2224/05657 , H01L2224/1147 , H01L2224/11474 , H01L2224/11901 , H01L2224/11902 , H01L2224/13007 , H01L2224/13023 , H01L2224/1308 , H01L2224/13083 , H01L2224/131 , H01L2224/13111 , H01L2224/13139 , H01L2224/13147 , H01L2224/13155 , H01L2224/13157 , H01L2224/13164 , H01L2224/16 , H01L2224/81191 , H01L2224/81801 , H01L2924/00013 , H01L2924/00014 , H01L2924/0002 , H01L2924/01005 , H01L2924/01014 , H01L2924/01022 , H01L2924/01023 , H01L2924/01027 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/01047 , H01L2924/0105 , H01L2924/01078 , H01L2924/01082 , H01L2924/01327 , H01L2924/014 , H01L2924/10253 , H01L2924/14 , H05K3/3436 , H05K2201/10242 , Y02P70/613 , H01L2224/13099 , H01L2224/29099 , H01L2924/00 , H01L2224/05552
摘要： An interconnect structure has a solder bump for attaching a die to a substrate. A cup shaped solder retaining part (70) retains at least part (90) of the solder in a non-spherical shape so that the bump extends from a surface of the die with a height greater than a diameter of the bump even after reflow. The bump can be formed by a stack of the solder retaining part and other layers of metal and solder (50). By shaping the solder, the spacing between bumps reduced. By shaping the solder to increase its height, the compliance of the bump is improved and thermally induced stress on the die is reduced.
摘要翻译：互连结构具有用于将管芯附接到衬底的焊料凸块。杯形焊料保持部分（70）将焊料的至少一部分（90）保持为非球形形状，使得即使在回流之后，凸起也从模具的表面延伸高度大于凸块的直径。凸块可以由焊料保持部分和其它金属和焊料层（50）的堆叠形成。通过成形焊料，凸块之间的间距减小。通过使焊料成形以增加其高度，凸起的顺应性得到改善，并且模具上的热致应力降低。

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