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1. 发明公开

EP3215931A1 VORRICHTUNG UND VERFAHREN ZUR MULTIPLIKATION ZUR ERSCHWERUNG VON SEITENKANALANGRIFFEN 有权
公开(公告)号：EP3215931A1
公开(公告)日：2017-09-13
申请号：EP15813693.7
申请日：2015-11-06
申请人： IHP GmbH-Innovations for High Performance Microelectronics / Leibniz-Institut für innovative Mikroelektronik
发明人： DYKA, Zoya , LANGENDÖRFER, Peter
IPC分类号： G06F7/53 , H04L9/00
CPC分类号： G06F7/5324 , G06F2207/7252 , G06F2207/7257 , H04L9/003 , H04L2209/08
摘要： The invention relates to a device for multiplying two bit sequences. A control unit selects exactly one multiplication unit from a plurality of multiplication units in dependence with a random signal and activates said multiplication unit. A partial multiplying unit used jointly by all multiplication units receives and multiplies operands, which are formed by respective activated multiplication units, with each other. Each of the multiplication units implements a different multiplication method for performing a multiplication and for this purpose has a selecting unit designed in accordance with the implemented multiplication method and an accumulating unit designed in accordance with the implemented multiplication method. Each selecting unit selects segments of the bit sequences step by step in accordance with a selection plan matched to the associated multiplication method, which bit sequences are to be multiplied, and forms operands from one or more segments and outputs said operands to the partial multiplying unit. Each accumulating unit receives, step by step, partial products output by the partial multiplying unit, accumulates said partial products in accordance with an accumulation plan matched to the implemented multiplication method and suitable for the selection plan, and outputs the product of the bit sequences, which has thus been determined, after the accumulation has been concluded.
摘要翻译：本发明涉及一种用于将两个比特序列相乘的装置。控制单元根据随机信号从多个乘法单元中恰好选择一个乘法单元并激活所述乘法单元。由所有乘法单元共同使用的部分乘法单元接收由相应激活的乘法单元形成的操作数并将它们彼此相乘。每个乘法单元实施用于执行乘法的不同乘法方法，并且为此具有根据所实现的乘法方法设计的选择单元和根据所实现的乘法方法设计的累加单元。每个选择单元按照与相关乘法方法相匹配的选择计划逐步地选择比特序列的片段，该比特序列将被相乘，并且从一个或多个片段形成操作数，并且将所述操作数输出到部分乘法单元。每个累加单元逐步地接收由部分乘法单元输出的部分乘积，根据与实现的乘法方法相匹配且适合于选择计划的累积计划累积所述部分乘积，并且输出位序列的乘积，因此在积累结束后已经确定。

2. 发明公开

EP2912687A1 INDIVIDUALISIERTE SPANNUNGSVERSORGUNG VON BAUELEMENTEN INTEGRIERTER SCHALTUNGEN ALS SCHUTZMAßNAHME GEGEN SEITENKANALANGRIFFE 有权
标题翻译：个性化的电源元器件集成电路AS防侧信道攻击的保护措施
公开(公告)号：EP2912687A1
公开(公告)日：2015-09-02
申请号：EP13795184.4
申请日：2013-10-25
申请人： IHP GmbH-Innovations for High Performance Microelectronics / Leibniz-Institut für innovative Mikroelektronik
发明人： DYKA, Zoya , LANGENDÖRFER, Peter
IPC分类号： H01L23/00 , H01L27/02
摘要： The invention relates to a semi-conductor device, in particular an integrated circuit with protection against side channel attacks, in particular imaging and probing based attacks, EMA and reverse engineering, in which a metallic conductive layer of a first (104) and/or second potential supply line (106) are directly linked to all circuit components, respectively individually via respective individual conductor path structures (V1, V2).

3. 发明公开

EP4207672A1 DUMMY PARTIAL MULTIPLICATION OF ZERO-OPERANDS AS A LOW-COST MEANS FOR REDUCING THE SUCCESS OF SCA ATTACKS AGAINST ECC 有权
公开(公告)号：EP4207672A1
公开(公告)日：2023-07-05
申请号：EP22168962.3
申请日：2022-04-20
申请人： IHP GmbH - Innovations for High Performance Microelectronics / Leibniz-Institut für innovative Mikroelektronik
发明人： KABIN, Ievgen , DYKA, Zoya , KLANN, Dan , LANGENDÖRFER, Peter
IPC分类号： H04L9/00 , H04L9/30
摘要： A device for performing accelerated elliptic curve point multiplication determines for each of the iterations of a main loop operation sequence a respective set of respective dummy clock cycle positions, and controls computational blocks to perform a partial multiplication of zero-operands in dummy clock cycles corresponding to the respective determined dummy clock cycle positions of the set of dummy clock cycle positions for the respective main loop iteration. For any of the sets that has two or more dummy clock cycle positions within the same main loop iteration, each two of the dummy clock cycle positions are separated from each other by at least one clock cycle of performing a partial multiplication of non-zero operands, and at least two of the sets of the dummy clock cycle positions differ from each other.

4. 发明授权

EP2649515B1 UNIFIZIERTER MULTIPLIZIERER FÜR DIE GALOIS-KÖRPER GF(2n) UND GF(p), SOWIE KRYPTOGRAPHIE-VERFAHREN UND KRYPTOGRAPHIE-VORRICHTUNG 有权
标题翻译：，统一乘法器BODY伽罗瓦GF（2n个）AND GF（p）和密码处理和密码术设备
公开(公告)号：EP2649515B1
公开(公告)日：2016-03-30
申请号：EP11787665.6
申请日：2011-11-16
申请人： IHP GmbH-Innovations for High Performance Microelectronics / Leibniz-Institut für innovative Mikroelektronik
发明人： DYKA, Zoya , LANGENDÖRFER, Peter
IPC分类号： G06F7/72
CPC分类号： G06F7/724

6. 发明授权

EP3215931B1 VORRICHTUNG UND VERFAHREN ZUR MULTIPLIKATION ZUR ERSCHWERUNG VON SEITENKANALANGRIFFEN 有权
公开(公告)号：EP3215931B1
公开(公告)日：2018-09-26
申请号：EP15813693.7
申请日：2015-11-06
申请人： IHP GmbH-Innovations for High Performance Microelectronics / Leibniz-Institut für innovative Mikroelektronik
发明人： DYKA, Zoya , LANGENDÖRFER, Peter
IPC分类号： G06F7/53 , H04L9/00
CPC分类号： G06F7/5324 , G06F2207/7252 , G06F2207/7257 , H04L9/003 , H04L2209/08

7. 发明公开

EP2649515A2 UNIFIZIERTER MULTIPLIZIERER FÜR DIE GALOIS-KÖRPER GF(2n) UND GF(p), SOWIE KRYPTOGRAPHIE-VERFAHREN UND KRYPTOGRAPHIE-VORRICHTUNG 有权
标题翻译：，统一乘法器BODY伽罗瓦GF（2n个）AND GF（p）和密码处理和密码术设备
公开(公告)号：EP2649515A2
公开(公告)日：2013-10-16
申请号：EP11787665.6
申请日：2011-11-16
申请人： IHP GmbH-Innovations for High Performance Microelectronics / Leibniz-Institut für innovative Mikroelektronik
发明人： DYKA, Zoya , LANGENDÖRFER, Peter
IPC分类号： G06F7/72
CPC分类号： G06F7/724
摘要： The invention relates to a device for determining a product C of two factors in the form of finite bit sequences A = a
n-1 a
n-2 ...a
1 a
0 and B = b
n-1 b
n-2 ...b
1 b
0 as a product optionally in the Galois field GF(p) or as a product in the Galois field GF(2
n ). The invention also relates to cryptographic methods and devices.

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