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1. 发明授权

EP3126959B1 ELLIPTIC CURVE POINT MULTIPLICATION PROCEDURE RESISTANT TO SIDE-CHANNEL INFORMATION LEAKAGE 有权
标题翻译：椭圆曲线点乘法程序抗侧信道信息泄漏
公开(公告)号：EP3126959B1
公开(公告)日：2018-02-28
申请号：EP15717339.4
申请日：2015-03-31
申请人： Qualcomm Incorporated
发明人： JACOBSON, David Merrill , BRUMLEY, Billy Bob
IPC分类号： G06F7/72 , H04L9/00
CPC分类号： H04L9/3066 , G06F7/725 , G06F2207/7257 , H04L9/003 , H04L2209/24 , H04L2209/72
摘要： One feature pertains to elliptic curve (EC) point multiplication for use in generating digital signatures. In one aspect, a scalar multiplier (k) of a base point (P) of order (n) is selected on an elliptic curve for use with EC point multiplication. An integer value (r) is then randomly generated from within a range of values constrained so that, regardless of the particular value of (r) obtained within the range, EC point multiplication procedures performed using the scalar multiplier (k) summed with a product of the integer multiplier (r) and the order (n) consume device resources independent of the value of the scalar multiplier (k) to thereby reduce or eliminate side-channel leakage. This may be achieved by determining the range of values for r so that the bit position of the most significant bit of k+(r*n) will be even and fixed for a particular elliptic curve.

2. 发明公开

EP2401734A1 SYSTEM AND METHOD FOR PERFORMING EXPONENTIATION IN A CRYPTOGRAPHIC SYSTEM 有权
标题翻译：系统和方法用于进行增强在密码系统
公开(公告)号：EP2401734A1
公开(公告)日：2012-01-04
申请号：EP10745753.3
申请日：2010-02-18
申请人： Certicom Corp.
发明人： EBEID, Nevine Maurice Nassif , LAMBERT, Robert John
IPC分类号： G09C5/00 , G06F7/72 , H04L9/28
CPC分类号： G06F7/723 , G06F2207/7233 , G06F2207/7247 , G06F2207/7257 , H04L9/004 , H04L9/3249
摘要： There are disclosed systems and methods for computing an exponentiated message. In one embodiment blinding is maintained during the application of a Chinese Remainder Theorem (CRT) algorithm and then removed subsequent to the completion of the CRT algorithm. In another embodiment, fault injection attacks, such as the gcd attack, can be inhibited by applying and retaining blinding during the application of the CRT algorithm to yield a blinded exponentiation value, and then subsequently removing the blinding in a manner that causes an error injected into the CRT computation to cascade into the exponent of the value used to unblind the blinded exponentiated value.

3. 发明公开

EP1652336A1 PROCEDE POUR LA MISE EN OEUVRE SECURISEE D'UN ALGORITHME DE CRYPTOGRAPHIE DE TYPE RSA ET COMPOSANT CORRESPONDANT 有权
标题翻译：方法RSA密码算法的安全的应用方法，在这方面与砌块。
公开(公告)号：EP1652336A1
公开(公告)日：2006-05-03
申请号：EP04741978.3
申请日：2004-07-08
申请人： GEMPLUS
发明人： VILLEGAS, Karine , JOYE, Marc , CHEVALLIER-MAMES, Benoit
IPC分类号： H04L9/30
CPC分类号： G06F7/723 , G06F2207/7242 , G06F2207/7257 , G06F2207/7271 , H04L9/003 , H04L9/004 , H04L9/302 , H04L2209/26
摘要： The invention relates to a method for the secure application of a cryptographic algorithm of the RSA type in an electronic component. The method permits obtaining the value of a public exponent e from a given set of probable values, without a priori knowledge of said value and, having determined said value for the public exponent e, permits the application of counter-measures using the value of e, to block error attacks and side channel attacks, particularly of the DPA and SPA type, which may be carried out on the application of a private operation of the cryptographic algorithm.

4. 发明公开

EP2758893A4 MODULAR EXPONENTIATION WITH PARTITIONED AND SCATTERED STORAGE OF MONTGOMERY MULTIPLICATION RESULTS 审中-公开
标题翻译：蒙哥马利乘积结果分区和分散存储模幂
公开(公告)号：EP2758893A4
公开(公告)日：2015-05-27
申请号：EP12833099
申请日：2012-09-10
申请人： INTEL CORP
发明人： GEURON SHAY , KRASNOV VLAD
IPC分类号： G06F7/72
CPC分类号： G06F7/723 , G06F7/728 , G06F2207/7257
摘要： Embodiments of techniques and systems for side-channel-protected modular exponentiation are described. In embodiments, during a modular exponentiation calculation, Montgomery Multiplication (“MM”) results are produced. These MM results are scattered through a table for storage, such that storage of the values may not lead to discovery of a secret exponent value by a spy process through a side-channel attack. The scattering may be performed in order to reduce a number of per-result memory operations performed during each MM result storage or retrieval. In embodiments, a window size of 4 may be used in the modular exponentiation, along with partitioning of the MM result into 32-bit partition values which are scattered with offsets of 64-bytes. In embodiments, while use of a window size of 4 may result in additional MM calculations during modular exponentiation than other window sizes, the reduction in memory operations may provide a positive performance offset.

5. 发明公开

EP2081316A1 CRYPTOGRAPHIC CALCULATION PROCESSING CIRCUIT 审中-公开
标题翻译：密码计算处理电路
公开(公告)号：EP2081316A1
公开(公告)日：2009-07-22
申请号：EP07767167.5
申请日：2007-06-19
申请人： Panasonic Corporation
发明人： YOSHIMOTO, Tetsuro , TANAKA, Takayuki
IPC分类号： H04L9/06
CPC分类号： G06F21/75 , G06F7/38 , G06F9/30003 , G06F9/30007 , G06F9/3836 , G06F21/72 , G06F2207/7219 , G06F2207/7257 , H04L9/003 , H04L2209/08 , H04L2209/12
摘要： A dummy operation instruction circuit (100) is provided for issuing a dummy operation instruction (113) to a cryptographic control circuit (101) instead of a CPU (109) or the like after being notified of execution of a cryptographic operation instruction (111) from the CPU (109) or the like. By causing operation resources (103 to 108), such as a memory, an operator, a register and the like, after the execution of the cryptographic operation instruction (111), though they are normally inactivated for that period, so that a current is consumed, it is difficult to identify timing of the end, start and the like of a cryptographic operation process based on the magnitude of a consumed current. The dummy operation instruction (113) is issued only for a period of time for which the cryptographic operation instruction (111) is not issued from the CPU (109) or the like. Therefore, the performance of the cryptographic operation process is not deteriorated.
摘要翻译：虚拟操作指令电路（100）被提供用于在被通知执行密码操作指令（111）之后向虚拟操作指令（113）而不是CPU（109）等发送到密码控制电路（101）来自CPU（109）等。通过在密码运算指令（111）的执行后使存储器，操作员，寄存器等运算资源（103〜108）正常地在该期间停止，从而电流成为消耗的情况下，难以基于消耗电流的大小来确定密码运算处理的结束时刻，开始时刻等。虚拟操作指令（113）仅在未从CPU（109）等发出密码操作指令（111）的时间段发布。因此，密码操作过程的性能不会恶化。

6. 发明公开

EP1946205A1 A METHOD FOR SCALAR MULTIPLICATION IN ELLIPTIC CURVE GROUPS OVER PRIME FIELDS FOR SIDE-CHANNEL ATTACK RESISTANT CRYPTOSYSTEMS 有权
标题翻译：方法分组标在主要领域SIDE椭圆曲线频攻击性KRYPTO系统
公开(公告)号：EP1946205A1
公开(公告)日：2008-07-23
申请号：EP05797792.8
申请日：2005-10-18
申请人： Telecom Italia S.p.A.
发明人： GOLIC, Jovan
IPC分类号： G06F7/72
CPC分类号： G06F7/725 , G06F7/721 , G06F7/728 , G06F2207/7257 , G06F2207/7261
摘要： A method for transforming data with a secret parameter in an elliptic curve cryptosystem based on an elliptic curve defined over an underlying prime field, the method comprising multiplying a point of the elliptic curve, representing the data to be transformed, by a scalar representing the secret parameter, wherein the multiplying includes performing at least one point addition operation and at least one point doubling operation on points of the elliptic curve. The method includes: providing a representation in affine coordinates of the elliptic curve point to be multiplied, and a representation in projective coordinates of intermediate elliptic curve points obtained during said multiplying; performing both the point addition operation and the point doubling operation by means of a sequence of elementary prime field operation types, the elementary prime field operation types including: a first type of prime field operations including field multiplication and field squaring of coordinates of the elliptic curve points, and a second type of prime field operations including field addition, field doubling, and field subtraction of coordinates of the elliptic curve points. A device is also provided, for transforming data with a secret parameter, comprising an integrated circuit adapted to perform the above mentioned method.

7. 发明公开

EP1050133A1 LEAK-RESISTANT CRYPTOGRAPHIC METHOD AND APPARATUS 有权
标题翻译：防漏KRYPTO图形的方法和装置
公开(公告)号：EP1050133A1
公开(公告)日：2000-11-08
申请号：EP98966880.1
申请日：1998-12-31
申请人： Cryptography Research Inc.
发明人： KOCHER, Paul, C. , JAFFE, Joshua, M.
IPC分类号： H04L9/30
CPC分类号： H04L9/3247 , G06F7/723 , G06F21/556 , G06F21/602 , G06F21/755 , G06F2207/7219 , G06F2207/7257 , G06Q20/367 , G06Q20/401 , H04L9/002 , H04L9/0841 , H04L9/0891 , H04L9/3013 , H04L9/302 , H04L63/1441 , H04L2209/56
摘要： The present invention provides a method and apparatus for securing cryptographic devices against attacks involving external monitoring and analysis. A 'self-healing' property is introduced, enabling security to be continually re-established following partial compromises. In addition to producing useful cryptographic results, a typical leak-resistant cryptographic operation modifies or updates (330) secret key material in a manner designed to render useless any information about the secrets that may have previously leaked from the system. Exemplary leak-proof and leak-resistant implementations of the invention are shown for symmetric authentication (350), certified Diffie-Hellman (when either one or both users have certificates), RSA, ElGamal public key decryption (303).

8. 发明公开

EP1006492A1 Information processing equipment and IC card 审中-公开
标题翻译： Datenverarbeitungsanlage und-chipkarte
公开(公告)号：EP1006492A1
公开(公告)日：2000-06-07
申请号：EP99123518.5
申请日：1999-11-25
申请人： Hitachi, Ltd.
发明人： Oki, Masaru, c/o HITACHI, Ltd. , Fukuzawa, Yasuko, c/o HITACHI, Ltd. , Okuhara, Susumu, c/o HITACHI, Ltd. , Kaminaga, Masahiro, c/o HITACHI, Ltd.
IPC分类号： G07F7/10 , G06F1/00 , G06K19/073
CPC分类号： G06F9/3838 , G06F7/72 , G06F7/721 , G06F7/723 , G06F9/3836 , G06F9/3885 , G06F2207/7233 , G06F2207/7247 , G06F2207/7252 , G06F2207/7257 , G06K19/07363 , G06Q20/341 , G06Q20/367 , G07F7/082 , G07F7/1008 , H04L9/003 , H04L2209/08 , H04L2209/127
摘要： An IC card (101) having a storage memory (204) including a program storage unit for storing a program and a data storage unit for storing data and a central processing unit (201) for executing a predetermined process in accordance with the program to process the data, the program including one or more data process units each having a process instruction for giving an execution instruction to the central processing unit, wherein a data process order is randomly exchanged and a dummy process is added to thereby reduce the dependency of consumption current of an IC chip upon the data process.
摘要翻译：一种具有存储存储器（204）的IC卡（101），包括用于存储程序的程序存储单元和用于存储数据的数据存储单元，以及用于根据程序执行预定处理的中央处理单元（201）所述数据，所述程序包括一个或多个数据处理单元，每个数据处理单元具有用于向中央处理单元发送执行指令的处理指令，其中随机地交换数据处理顺序并添加虚拟处理，从而减少消耗电流的依赖性的IC芯片。

9. 发明公开

EP3215931A1 VORRICHTUNG UND VERFAHREN ZUR MULTIPLIKATION ZUR ERSCHWERUNG VON SEITENKANALANGRIFFEN 有权
公开(公告)号：EP3215931A1
公开(公告)日：2017-09-13
申请号：EP15813693.7
申请日：2015-11-06
申请人： IHP GmbH-Innovations for High Performance Microelectronics / Leibniz-Institut für innovative Mikroelektronik
发明人： DYKA, Zoya , LANGENDÖRFER, Peter
IPC分类号： G06F7/53 , H04L9/00
CPC分类号： G06F7/5324 , G06F2207/7252 , G06F2207/7257 , H04L9/003 , H04L2209/08
摘要： The invention relates to a device for multiplying two bit sequences. A control unit selects exactly one multiplication unit from a plurality of multiplication units in dependence with a random signal and activates said multiplication unit. A partial multiplying unit used jointly by all multiplication units receives and multiplies operands, which are formed by respective activated multiplication units, with each other. Each of the multiplication units implements a different multiplication method for performing a multiplication and for this purpose has a selecting unit designed in accordance with the implemented multiplication method and an accumulating unit designed in accordance with the implemented multiplication method. Each selecting unit selects segments of the bit sequences step by step in accordance with a selection plan matched to the associated multiplication method, which bit sequences are to be multiplied, and forms operands from one or more segments and outputs said operands to the partial multiplying unit. Each accumulating unit receives, step by step, partial products output by the partial multiplying unit, accumulates said partial products in accordance with an accumulation plan matched to the implemented multiplication method and suitable for the selection plan, and outputs the product of the bit sequences, which has thus been determined, after the accumulation has been concluded.
摘要翻译：本发明涉及一种用于将两个比特序列相乘的装置。控制单元根据随机信号从多个乘法单元中恰好选择一个乘法单元并激活所述乘法单元。由所有乘法单元共同使用的部分乘法单元接收由相应激活的乘法单元形成的操作数并将它们彼此相乘。每个乘法单元实施用于执行乘法的不同乘法方法，并且为此具有根据所实现的乘法方法设计的选择单元和根据所实现的乘法方法设计的累加单元。每个选择单元按照与相关乘法方法相匹配的选择计划逐步地选择比特序列的片段，该比特序列将被相乘，并且从一个或多个片段形成操作数，并且将所述操作数输出到部分乘法单元。每个累加单元逐步地接收由部分乘法单元输出的部分乘积，根据与实现的乘法方法相匹配且适合于选择计划的累积计划累积所述部分乘积，并且输出位序列的乘积，因此在积累结束后已经确定。

10. 发明公开

EP2401734A4 SYSTEM AND METHOD FOR PERFORMING EXPONENTIATION IN A CRYPTOGRAPHIC SYSTEM 有权
标题翻译：系统和方法用于进行增强在密码系统
公开(公告)号：EP2401734A4
公开(公告)日：2014-03-19
申请号：EP10745753
申请日：2010-02-18
申请人： CERTICOM CORP
发明人： EBEID NEVINE MAURICE NASSIF , LAMBERT ROBERT JOHN
IPC分类号： G09C5/00 , G06F7/72 , H04L9/00 , H04L9/28 , H04L9/32
CPC分类号： G06F7/723 , G06F2207/7233 , G06F2207/7247 , G06F2207/7257 , H04L9/004 , H04L9/3249

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