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1. 发明公开

EP0902358A3 Division circuit and method 失效
标题翻译： Dividierschaltung und -verfahren
公开(公告)号：EP0902358A3
公开(公告)日：2002-01-02
申请号：EP98120014.0
申请日：1992-06-22
申请人： Hitachi, Ltd. , Hitachi ULSI Systems Co.,Ltd.
发明人： Kawasaki, Shumpei , Sakakibara, Eiji , Fukada, Kaoru , Yamazaki, Takanaga , Akao, Yasushi , Baba, Shiro , Kihara, Toshimasa , Kurakazu, Keiichi , Tsukamoto, Takashi , Masumura, Shigeki , Tawara, Yasuhiro , Kashiwagi, Yugo , Fujita, Shuya , Ishida, Katsuhiko , Noriko, Sawa , Asano, Yoichi , Chaki, Hideaki , Sugawara, Tadahiko , Kainaga, Masahiro , Noguchi, Kouki , Watabe, Mitsuru
IPC分类号： G06F7/52
CPC分类号： G06F7/535 , G06F9/30 , G06F9/3001 , G06F9/30112 , G06F9/3013 , G06F9/30145 , G06F9/30149 , G06F9/3016 , G06F9/30163 , G06F9/30167 , G06F9/30181 , G06F9/30189 , G06F9/322 , G06F9/324 , G06F9/3557 , G06F9/3802 , G06F9/3814 , G06F9/3836 , G06F9/3857 , G06F9/3859 , G06F9/3867 , G06F2207/5352
摘要： A circuit and method for performing signed integer division by repeated division processing, in which a new partial remainder is formed by subtracting (or adding) a divisor from (to) a dividend or a partial remainder in accordance with the sign of the dividend or the partial remainder and the sign of the divisor, and a quotient bit is formed on the basis of the sign of the partial remainder and the sign of the divisor, wherein a pre-processing step corrects the dividend by subtracting 1 from the dividend if it is negative, and a post-processing step corrects the quotient formed by the repeated division processing on the basis of its sign.
摘要翻译： RISC型微处理器的固定结构长度为2 n位，数据使用大小为2 m，m大于或等于n。

2. 发明授权

EP0525375B1 Microcomputer 失效
标题翻译：微电脑
公开(公告)号：EP0525375B1
公开(公告)日：2001-11-28
申请号：EP92110517.7
申请日：1992-06-22
申请人： Hitachi, Ltd. , Hitachi ULSI Systems Co.,Ltd.
发明人： Kawasaki, Shumpei , Sakakibara, Eiji , Fukada, Kaoru , Yamazaki, Takanaga , Akao, Yasushi , Baba, Shiro , Kihara, Toshimasa , Kurakazu, Keiichi , Tsukamoto, Takashi , Masumura, Shigeki , Tawara, Yasuhiro , Kashiwagi, Yugo , Fujita, Shuya , Ishida, Katsuhiko , Sawa, Noriko , Asano, Yoichi , Chaki, Hideaki , Sugawara, Tadahiko , Kainaga, Masahiro , Noguchi, Kouki , Watabe, Mitsuru
IPC分类号： G06F9/38
CPC分类号： G06F7/535 , G06F9/30 , G06F9/3001 , G06F9/30112 , G06F9/3013 , G06F9/30145 , G06F9/30149 , G06F9/3016 , G06F9/30163 , G06F9/30167 , G06F9/30181 , G06F9/30189 , G06F9/322 , G06F9/324 , G06F9/3557 , G06F9/3802 , G06F9/3814 , G06F9/3836 , G06F9/3857 , G06F9/3859 , G06F9/3867 , G06F2207/5352
摘要： RISC-type microprocessor has a fixed struction lenght of 2 bits, whilst the data use size is 2 bits,where m is greater than or equal to n.

3. 发明授权

EP0902361B1 Single-chip microcomputer 失效
标题翻译：单片机
公开(公告)号：EP0902361B1
公开(公告)日：2004-06-02
申请号：EP98120015.7
申请日：1992-06-22
申请人： Hitachi, Ltd. , Hitachi ULSI Systems Co.,Ltd.
发明人： Kawasaki, Shumpei , Sakakibara, Eiji , Fukada, Kaoru , Yamazaki, Takanaga , Akao, Yasushi , Baba, Shiro , Kihara, Toshimasa , Kurakazu, Keiichi , Tsukamoto, Takashi , Masumura, Shigeki , Tawara, Yasuhiro , Kashiwagi, Yugo , Fujita, Shuya , Ishida, Katsuhiko , Sawa, Noriko , Asano, Yoichi , Chaki, Hideaki , Sugawara, Tadahiko , Kainaga, Masahiro , Noguchi, Kouki , Watabe, Mitsuru
IPC分类号： G06F9/38 , G06F15/78
CPC分类号： G06F7/535 , G06F9/30 , G06F9/3001 , G06F9/30112 , G06F9/3013 , G06F9/30145 , G06F9/30149 , G06F9/3016 , G06F9/30163 , G06F9/30167 , G06F9/30181 , G06F9/30189 , G06F9/322 , G06F9/324 , G06F9/3557 , G06F9/3802 , G06F9/3814 , G06F9/3836 , G06F9/3857 , G06F9/3859 , G06F9/3867 , G06F2207/5352
摘要： RISC-type microprocessor has a fixed struction lenght of 2 bits, whilst the data use size is 2 bits,where m is greater than or equal to n.

4. 发明公开

EP0902361A3 Single-chip CPU and microcomputer 失效
标题翻译：单片CPU和单片机
公开(公告)号：EP0902361A3
公开(公告)日：2002-01-02
申请号：EP98120015.7
申请日：1992-06-22
申请人： Hitachi, Ltd. , Hitachi ULSI Systems Co.,Ltd.
发明人： Kawasaki, Shumpei , Sakakibara, Eiji , Fukada, Kaoru , Yamazaki, Takanaga , Akao, Yasushi , Baba, Shiro , Kihara, Toshimasa , Kurakazu, Keiichi , Tsukamoto, Takashi , Masumura, Shigeki , Tawara, Yasuhiro , Kashiwagi, Yugo , Fujita, Shuya , Ishida, Katsuhiko , Sawa, Noriko , Asano, Yoichi , Chaki, Hideaki , Sugawara, Tadahiko , Kainaga, Masahiro , Noguchi, Kouki , Watabe, Mitsuru
IPC分类号： G06F9/38 , G06F15/78
CPC分类号： G06F7/535 , G06F9/30 , G06F9/3001 , G06F9/30112 , G06F9/3013 , G06F9/30145 , G06F9/30149 , G06F9/3016 , G06F9/30163 , G06F9/30167 , G06F9/30181 , G06F9/30189 , G06F9/322 , G06F9/324 , G06F9/3557 , G06F9/3802 , G06F9/3814 , G06F9/3836 , G06F9/3857 , G06F9/3859 , G06F9/3867 , G06F2207/5352
摘要： A microcomputer MCU adopting the general purpose register method is enabled to have a small program capacity or a high program memory using efficiency and low system cost, while enjoying the advantage of simplification of the instruction decoding as in the RISC machine having a fixed length instruction format of the prior art, by adopting an instruction format of a fixed length of 2 n bits which is smaller than the length of the maximum data word fed to instruction execution means. The control of the coded division is executed by noting the code bits.
摘要翻译：采用通用寄存器方法的微型计算机MCU能够具有小的程序容量或高程序存储器使用效率和低系统成本，同时享有如具有固定长度指令格式的RISC机器中的简化指令解码的优点通过采用比输入指令执行装置的最大数据字的长度小的固定长度2n比特的指令格式，编码部分的控制是通过记录码位来执行的。

5. 发明授权

EP0646873B1 Single-chip microcomputer 失效
标题翻译： Einchip-Mikrorechner
公开(公告)号：EP0646873B1
公开(公告)日：2008-10-08
申请号：EP94112520.5
申请日：1994-08-10
申请人： Hitachi, Ltd. , Hitachi ULSI Systems Co.,Ltd.
发明人： Kawasaki, Shumpei , Akao, Yasushi , Noguchi, Kouki , Hasegawa, Atsushi , Ohsuga, Hiroshi , Kurakazu, Keiichi , Matsubara, Kiyoshi , Hayakawa, Akio , Ito, Yoshitaka
IPC分类号： G06F13/40 , G06F15/78 , G06F12/08 , G06F13/42
CPC分类号： G06F9/3001 , G06F12/0893 , G06F13/36 , G06F13/405 , G06F15/7817 , H04W28/08 , H04W52/0216 , H04W88/02 , Y02D10/12 , Y02D10/13 , Y02D10/14 , Y02D10/151 , Y02D70/142 , Y02D70/26
摘要： A single-chip microcomputer comprising: a first bus having a central processing unit and a cache memory connected therewith; a second bus having a dynamic memory access control circuit and an external bus interface connected therewith; a break controller for connecting the first bus and the second bus selectively; a third bus having a peripheral module connected therewith and having a lower-speed bus cycle than the bus cycles of the first and second buses; and a bus state controller for effecting a data transfer and a synchronization between the second bus and the third bus. The single-chip microcomputer has the three divided internal buses to reduce the load capacity upon the signal transmission paths so that the signal transmission can be accomplished at a high speed. Moreover, the peripheral module required to have no operation speed is isolated so that the power dissipation can be reduced.
摘要翻译：一种单片微计算机，包括：具有中央处理单元和与其连接的高速缓冲存储器的第一总线; 具有动态存储器访问控制电路和与其连接的外部总线接口的第二总线; 用于选择性地连接第一总线和第二总线的断开控制器; 第三总线具有与其连接的外围模块，并且具有比第一和第二总线的总线周期更低的总线周期; 以及用于进行数据传送和第二总线与第三总线之间的同步的总线状态控制器。单片机具有三条分开的内部总线，以减少信号传输路径上的负载能力，从而可以高速实现信号传输。此外，隔离所需要的没有运行速度的外围模块，从而可以降低功耗。

6. 发明公开

EP0598704A2 Bus error processing system 失效
标题翻译： Busfehlerverarbeitungssystem。
公开(公告)号：EP0598704A2
公开(公告)日：1994-05-25
申请号：EP94101525.7
申请日：1988-08-17
申请人： HITACHI, LTD.
发明人： Maruyama, Takashi , Kurakazu, Keiichi , Kaneko, Susumu , Kida, Hiroyuki
IPC分类号： G06F11/00 , G06F13/28
CPC分类号： G06F11/0745 , G06F11/0793
摘要： A bus error ascribable to a bus master module (2) other than a central processing unit (CPU) (1) is set as a specified factor for an exception process. When the exception process is requested, the CPU (1) executes a corresponding service program for the exception process without executing a process for altering and setting mask bits, which would be executed for a normal interrupt request. Thus, the exception process request specific to the bus error is not undesirably refused by interrupt requests etc., being accepted before the bus error. Furthermore there is a reduction in the time which is expended before the start of the run of a service program corresponding to the bus error, with the result that the reliability of the process for the bus error attributed to the predetermined bus master module (2) other than the CPU (1) is enhanced.
摘要翻译：作为除了中央处理单元（CPU）（1）以外的总线主模块（2）的总线误差被设定为异常处理的规定因素。当请求异常处理时，CPU（1）执行用于异常处理的相应服务程序，而不执行用于更改和设置将对正常中断请求执行的掩码位的处理。因此，专用于总线错误的异常处理请求不会被中断请求等拒绝，在总线错误之前被接受。此外，在对应于总线错误的服务程序的运行开始之前消耗的时间减少，结果是归因于预定总线主模块（2）的总线错误的处理的可靠性，除了CPU（1）之外，增强了。

7. 发明公开

EP0312194A3 Data processor having two modes of operation 失效
标题翻译：具有两种操作模式的数据处理器
公开(公告)号：EP0312194A3
公开(公告)日：1991-04-24
申请号：EP88307303.3
申请日：1988-08-08
申请人： HITACHI, LTD.
发明人： Kaneko, Susumu , Kurakazu, Keiichi
IPC分类号： G06F9/46 , G06F12/14
CPC分类号： G06F21/74 , G06F9/45533 , G06F12/1458
摘要： A microcomputer has program execution states including a supervisor state and a user state. A flag (ALV) or a register (RCR1) having such a flag (ALV) indicates whether or not a RAM area (1) used in the supervisor state can be used in the user state by the CPU and a judge circuit (13) determines whether or not the CPU has made an attempt invalidly to access the RAM (1) in the user state based on the content of the flag (ALV) or the register (RCR1) and that of a supervisor/user state specify bit (S/U) in the status register (SR). When an access violation has occurred, a violation signal is sent to the CPU and the selection signal of the RAM (1) is disabled, thereby increasing the reliability of the system.

8. 发明公开

EP0220684A3 Data processing system 失效
标题翻译：数据处理系统
公开(公告)号：EP0220684A3
公开(公告)日：1989-12-13
申请号：EP86114724.7
申请日：1986-10-23
申请人： HITACHI, LTD.
发明人： Kurakazu, Keiichi , Baba, Shiro
IPC分类号： G06F9/34 , G06F9/30
CPC分类号： G06F9/30192
摘要： An instruction having two operands including a field (Sz2) specifying the bit length of a source operand and a field (Sz1) specifying the bit length of data to be operated by the execution unit. Based on size information stored in these fields (Sz1, Sz2), the operand bit length is modified, which unnecessitates the modification of the bit length of an operand by use of a macro instruction Consequently, the program execution speed can be improved.
摘要翻译：具有两个操作数的指令，包括指定源操作数的位长的字段（Sz2）和指定要由执行单元操作的数据的位长的字段（Sz1）。根据存储在这些字段（Sz1，Sz2）中的大小信息，操作数位长度被修改，这不需要通过使用宏指令来修改操作数的位长。因此，可以提高程序执行速度。

9. 发明授权

EP0517282B1 Register allocation in an information processing apparatus 失效
标题翻译：在信息处理装置的寄存器分配
公开(公告)号：EP0517282B1
公开(公告)日：1999-07-28
申请号：EP92110395.8
申请日：1987-04-14
申请人： Hitachi, Ltd.
发明人： Watanabe, Tan , Kurakazu, Keiichi , Kashiwagi, Yugo , Toyama, Keisuke , Nojiri, Tohru
IPC分类号： G06F9/46
CPC分类号： G06F9/30138 , G06F9/30105 , G06F9/30127 , G06F9/30134 , G06F9/342 , G06F9/4484 , G06F9/461 , G06F9/462
摘要： In a computer system equipped with a large number of registers (R, Q) which have an access time much shorter than that of a main memory, a register designating address part (12) in which the assignment (13) of an area register (21) having a register address (i) of a register area as its value and the assignment (14) of a register displacement value (d) expressing a relative register address within the register area are combined is provided in each instruction so that, even when physical registers are increased, save and restore of registers attendant upon task switches, etc. may be lessened to attain a raised speed of program run processing. Besides, an address part (103) for designating the main memory is provided in the same instruction.

10. 发明公开

EP0646873A2 Single-chip microcomputer 失效
标题翻译：单片机。
公开(公告)号：EP0646873A2
公开(公告)日：1995-04-05
申请号：EP94112520.5
申请日：1994-08-10
申请人： HITACHI, LTD. , HITACHI MICROCOMPUTER SYSTEM LTD.
发明人： Kawasaki, Shumpei , Akao, Yasushi , Noguchi, Kouki , Hasegawa, Atsushi , Ohsuga, Hiroshi , Kurakazu, Keiichi , Matsubara, Kiyoshi , Hayakawa, Akio , Ito, Yoshitaka
IPC分类号： G06F13/40 , G06F15/78 , G06F12/08 , G06F13/42
CPC分类号： G06F9/3001 , G06F12/0893 , G06F13/36 , G06F13/405 , G06F15/7817 , H04W28/08 , H04W52/0216 , H04W88/02 , Y02D10/12 , Y02D10/13 , Y02D10/14 , Y02D10/151 , Y02D70/142 , Y02D70/26
摘要： A single-chip microcomputer comprising: a first bus having a central processing unit and a cache memory connected therewith; a second bus having a dynamic memory access control circuit and an external bus interface connected therewith; a break controller for connecting the first bus and the second bus selectively; a third bus having a peripheral module connected therewith and having a lower-speed bus cycle than the bus cycles of the first and second buses; and a bus state controller for effecting a data transfer and a synchronization between the second bus and the third bus. The single-chip microcomputer has the three divided internal buses to reduce the load capacity upon the signal transmission paths so that the signal transmission can be accomplished at a high speed. Moreover, the peripheral module required to have no operation speed is isolated so that the power dissipation can be reduced.

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