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1. 发明授权

EP0339922B1 Combined pulse rate/width modulation arrangement 失效
标题翻译：安排用于组合脉搏率和脉冲宽度调制
公开(公告)号：EP0339922B1
公开(公告)日：1998-03-04
申请号：EP89304090.7
申请日：1989-04-25
申请人： Hewlett-Packard Company
发明人： Bohley, Thomas K. , Garnett, Grosvenor H. , Koerner, Christopher , Moore, Charles E.
IPC分类号： H03M1/82 , H03M1/86
CPC分类号： H03M1/68 , H03M1/822 , H03M1/86

2. 发明公开

EP0568198A3 Integrated circuit for physiological signal measurement 失效
标题翻译：用于生理信号测量的集成电路
公开(公告)号：EP0568198A3
公开(公告)日：1994-09-21
申请号：EP93302548.8
申请日：1993-03-31
申请人： Hewlett-Packard Company
发明人： Baumgartner, Richard A. , Moore, Charles E. , Herleikson, Earl C.
IPC分类号： G01R19/25 , A61B5/0428
CPC分类号： H03F3/45968 , A61B5/7203 , G06F19/00 , G16H40/40 , G16H40/63 , H03F3/45188 , H03F3/45659 , H03F3/45775 , H03F2200/331
摘要： A mixed analog and digital integrated circuit for physiological signal instrumentation such as electrocardiographs, electromyographs, and electroencephalographs comprises analog signal amplifiers (126) connected to A/D converters (346) and an analog signal summer (122) for generating from analog averaging inputs (1300) an averaging output (336), and averaging switches (1302) which associate individual averaging inputs (1300) to the outputs of corresponding analog signal amplifiers (126) in dependence upon a digital averaging selection bits generated by a digital control (1902, 1904, 1906, 1912) in response to an external input (366). The integrated circuit has five signal channels, each with analog amplification and analog to digital conversion. The channels can be configured for various combinations of input signal amplification, input signal summation, analog output driving, and AC impedance measurement. The integrated circuit has two digital serial input lines and two digital serial output lines, all designed for direct connection to optical couplers. Channel configuration, gain, and other parameters are externally controllable by a serial digital input signal. Up to six compatible devices can be serially connected in a chain.

3. 发明公开

EP0521634A2 Improved thermal inkjet printhead structure and method for making the same 失效
标题翻译： Thermische Tintenstrahldruckkopfstruktur und Herstellungsverfahren。
公开(公告)号：EP0521634A2
公开(公告)日：1993-01-07
申请号：EP92305554.5
申请日：1992-06-17
申请人： Hewlett-Packard Company
发明人： Fasen, Duane A. , Beckmann, Jerome E. , Stanback, John H. , Hess, Ulrich E. , Metz, Larry S. , Moore, Charles E. , Hulings, James R.
IPC分类号： B41J2/16 , B41J2/34
CPC分类号： B41J2/14129 , B41J2/1603 , B41J2/1628 , B41J2/1629 , B41J2/1631 , B41J2/1642 , B41J2/1646 , B41J2202/03 , B41J2202/13 , Y10T29/49401
摘要： An improved thermal inkjet printhead having MOSFET drive transistors (126) incorporated therein. The gate (110) of each MOSFET transistor (126) is formed by applying a layer (72) of silicon dioxide onto a silicon substrate (70), applying a layer (76) of silicon nitride onto the silicon dioxide, and applying a layer (90) of polycrystalline silicon onto the silicon nitride. Portions of the substrate (70) surrounding the gate (110) are oxidized, forming field oxide regions (84, 86). Source and drain regions (118, 120) are then conventionally formed, followed by the application of a protective dielectric layer (124) onto the field oxide (84, 86), source (118), drain (120), and gate (110). A resistive layer (180) is deposited on the dielectric layer (124) and directly connected to the source (118), drain (120), and gate (110). A conductive layer (181) is deposited on a portion of the resistive layer (180), ultimately forming both uncovered and covered regions (202, 204, 206) thereof. The uncovered region (202) functions as a heating resistor (209), and the covered regions (204, 206) function as electrical contacts to the transistor (126) and resistor (209).
摘要翻译：一种改进的热喷墨打印头，其具有并入其中的MOSFET驱动晶体管（126）。每个MOSFET晶体管（126）的栅极（110）通过将二氧化硅层（72）施加到硅衬底（70）上，将氮化硅层（76）施加到二氧化硅上，并施加层（90）的多晶硅到氮化硅上。围绕栅极（110）的衬底（70）的部分被氧化，形成场氧化物区域（84,86）。然后通常形成源区和漏区（118,120），随后在场氧化物（84,86），源极（118），漏极（120）和栅极（110）上施加保护电介质层（124））。电阻层（180）沉积在电介质层（124）上并直接连接到源极（118），漏极（120）和栅极（110）。导电层（181）沉积在电阻层（180）的一部分上，最终形成其未覆盖区域和覆盖区域（202,204,206）。未覆盖区域（202）用作加热电阻器（209），并且覆盖区域（204,206）用作与晶体管（126）和电阻器（209）的电接触。

4. 发明授权

EP0568197B1 Biomedical amplifier circuit 失效
标题翻译：生物医学放大器电路
公开(公告)号：EP0568197B1
公开(公告)日：1999-01-07
申请号：EP93302547.0
申请日：1993-03-31
申请人： Hewlett-Packard Company
发明人： Baumgartner, Richard A. , Moore, Charles E.
IPC分类号： H03F1/30 , H03F3/45
CPC分类号： A61B5/0428 , A61B5/04004 , A61B5/7203 , A61B5/7242 , H03F3/45188 , H03F3/45475 , H03F3/4565 , H03F3/45659 , H03F3/45775 , H03F3/45941 , H03F3/45973 , H03F3/45995 , H03F2200/261 , H03F2200/331 , H03F2203/45644

5. 发明公开

EP0339922A3 Combined rate/width modulation arrangement 失效
标题翻译：组合速率/宽度调制安排
公开(公告)号：EP0339922A3
公开(公告)日：1992-01-15
申请号：EP89304090.7
申请日：1989-04-25
申请人： Hewlett-Packard Company
发明人： Bohley, Thomas K. , Garnett, Grosvenor H. , Koerner, Christopher , Moore, Charles E.
IPC分类号： H03M1/82 , H03M1/86
CPC分类号： H03M1/68 , H03M1/822 , H03M1/86
摘要： Pulse modulation circuitry which receives n binary data bits and generates a rate/width pulse modulated signal representing the binary value of the received data bits. The lower order m of the n bits generate a rate modulated signal having a number of pulses equal to the binary value of the m bits. The remainder of the n bits width modulate the rate modulated pulses. Each least significant bit increase in the binary value of the received date bits increases the width of a rate modulated pulse by a predetermined amount.

6. 发明公开

EP0339922A2 Combined rate/width modulation arrangement 失效
标题翻译： Anordnung zur kombinierten Raten / Breiten-Modulation。
公开(公告)号：EP0339922A2
公开(公告)日：1989-11-02
申请号：EP89304090.7
申请日：1989-04-25
申请人： Hewlett-Packard Company
发明人： Bohley, Thomas K. , Garnett, Grosvenor H. , Koerner, Christopher , Moore, Charles E.
IPC分类号： H03M1/82 , H03M1/86
CPC分类号： H03M1/68 , H03M1/822 , H03M1/86
摘要： Pulse modulation circuitry which receives n binary data bits and generates a rate/width pulse modulated signal representing the binary value of the received data bits. The lower order m of the n bits generate a rate modulated signal having a number of pulses equal to the binary value of the m bits. The remainder of the n bits width modulate the rate modulated pulses. Each least significant bit increase in the binary value of the received date bits increases the width of a rate modulated pulse by a predetermined amount.
摘要翻译：脉冲调制电路，其接收n个二进制数据位，并产生表示接收到的数据位的二进制值的速率/宽度脉冲调制信号。 n位的低阶m产生具有等于m位的二进制值的脉冲数的速率调制信号。 n位宽度的其余部分调制速率调制脉冲。接收日期位的二进制值中的每个最低有效位增加将速率调制脉冲的宽度增加预定量。

7. 发明公开

EP0957630A2 Column amplifier architecture in an active pixel sensor 有权
标题翻译： Spalteverstärkerarchitektur在einem aktiven Pixelsensor
公开(公告)号：EP0957630A2
公开(公告)日：1999-11-17
申请号：EP99303595.5
申请日：1999-05-07
申请人： Hewlett-Packard Company
发明人： Borg, Matthew M. , Moore, Charles E.
IPC分类号： H04N3/15 , H04N5/217
CPC分类号： H04N5/361 , H01L27/14609 , H01L27/14643 , H04N5/3575 , H04N5/378
摘要： A pixel column amplifier architecture creates a reduced noise differential image signal (118) from an pixel sensor array (280). The pixel column amplifier architecture comprises a first double sampling (DS) circuit (230) and a second DS circuit (240) that has the same configuration as the first DS circuit (230). An image signal (38) containing a combination of noise components (74) created on a substrate is coupled to the first DS circuit (230). A reference image signal (102), held in a reset state, represents the noise component of the image signal and is coupled to the second DS circuit (240). Further, a reference voltage source (88) is coupled to a reference input of both the first DS (230) and the second DS (240) circuits. The first DS circuit (230) provides the first side (120) of the differential image signal (118), and the second DS circuit (122) provides the second side of the differential image signal (118).
摘要翻译：像素列放大器架构从像素传感器阵列（280）创建降低的噪声差分图像信号（118）。像素列放大器架构包括具有与第一DS电路（230）相同配置的第一双采样（DS）电路（230）和第二DS电路（240）。包含在衬底上产生的噪声分量（74）的组合的图像信号（38）耦合到第一DS电路（230）。保持在复位状态的参考图像信号（102）表示图像信号的噪声分量，并耦合到第二DS电路（240）。此外，参考电压源（88）耦合到第一DS（230）和第二DS（240）电路的参考输入。第一DS电路（230）提供差分图像信号（118）的第一侧（120），并且第二DS电路（122）提供差分图像信号（118）的第二侧。

8. 发明公开

EP0571075A3 Analog to digital converter with autoranging offset 失效
标题翻译：具有自动模拟/数字转换器的偏移范围的控制。
公开(公告)号：EP0571075A3
公开(公告)日：1995-03-15
申请号：EP93302544.7
申请日：1993-03-31
申请人： HEWLETT-PACKARD COMPANY
发明人： Baumgartner, Richard A. , Moore, Charles E. , Herleikson, Earl C.
IPC分类号： H03M1/18 , H03F3/00 , G06G7/18
CPC分类号： H03M1/005 , A61B5/0428 , A61B5/7203 , A61B5/7242 , G06G7/1865 , H03F3/005 , H03F3/393 , H03F2200/261 , H03F2200/331 , H03M1/181 , H03M1/504 , H03M3/392 , H03M3/398 , H03M3/48 , H03M3/488
摘要： In a mixed analog and digital integrated circuit for physiological signal instrumentation such as electrocardiographs, electromyographs, and electroencephalographs, an AD converter (346) adds an analog signal input (416) to an analog offset input to produce a digital signal output (724), and an offset means (736,740) generates the analog offset input if the digital output exceeds a threshold (1006,1008) for a predetermined number of A/D conversion. The integrated circuit has five signal channels, each with analog amplification and analog to digital conversion. The channels can be configured for various combinations of input signal amplification, input signal summation, analog output driving, and AC impedance measurement. The integrated circuit has two digital serial input lines and two digital serial output lines, all designed for direct connection to optical couplers. Channel configuration, gain, and other parameters are externally controllable by a serial digital input signal. Up to six compatible devices can be serially connected in a chain.

9. 发明公开

EP0568199A3 Signal processing circuits with serial chaining 失效
标题翻译：具有串行链路的信号处理电路
公开(公告)号：EP0568199A3
公开(公告)日：1994-09-21
申请号：EP93302549.6
申请日：1993-03-31
申请人： Hewlett-Packard Company
发明人： Baumgartner, Richard A. , Moore, Charles E. , Herleikson, Earl. C.
IPC分类号： G06F15/42 , G01R19/25 , H03M1/18 , G05B19/00
CPC分类号： G05B19/042 , A61B5/0428 , A61B5/7203 , A61B5/7242 , G06F19/00 , G16H40/40 , G16H40/63
摘要： Mixed analog and digital integrated circuitry for physiological signal instrumentation such as electrocardiographs, electromyographs, and electroencephalographs comprises serially-connected circuits (1800,1802,1804) each comprising an A/D converter (346), a shift register (1924) for receiving, storing, shifting and outputting digital data (724) from the A/D converter (346) and a data clock (375) for clocking the shift register. The integrated circuit has five signal channels, each with analog amplification and analog to digital conversion. The channels can be configured for various combinations of input signal amplification, input signal summation, analog output driving, and AC impedance measurement. The integrated circuit has two digital serial input lines and two digital serial output lines, all designed for direct connection to optical couplers. Channel configuration, gain, and other parameters are externally controllable by a serial digital input signal. Up to six compatible devices can be serially connected in a chain.

10. 发明公开

EP0568199A2 Signal processing circuits with serial chaining 失效
标题翻译： Signalverarbeitungsschaltungen mit serieller Verkettung。
公开(公告)号：EP0568199A2
公开(公告)日：1993-11-03
申请号：EP93302549.6
申请日：1993-03-31
申请人： Hewlett-Packard Company
发明人： Baumgartner, Richard A. , Moore, Charles E. , Herleikson, Earl. C.
IPC分类号： G06F15/42 , G01R19/25 , H03M1/18 , G05B19/00
CPC分类号： G05B19/042 , A61B5/0428 , A61B5/7203 , A61B5/7242 , G06F19/00 , G16H40/40 , G16H40/63
摘要： Mixed analog and digital integrated circuitry for physiological signal instrumentation such as electrocardiographs, electromyographs, and electroencephalographs comprises serially-connected circuits (1800,1802,1804) each comprising an A/D converter (346), a shift register (1924) for receiving, storing, shifting and outputting digital data (724) from the A/D converter (346) and a data clock (375) for clocking the shift register. The integrated circuit has five signal channels, each with analog amplification and analog to digital conversion. The channels can be configured for various combinations of input signal amplification, input signal summation, analog output driving, and AC impedance measurement. The integrated circuit has two digital serial input lines and two digital serial output lines, all designed for direct connection to optical couplers. Channel configuration, gain, and other parameters are externally controllable by a serial digital input signal. Up to six compatible devices can be serially connected in a chain.
摘要翻译：用于诸如心电图仪，肌电描记器和脑电图仪的生理信号仪器的混合模拟和数字集成电路包括串联连接的电路（1800,1802,1804），每个电路包括A / D转换器（346），用于接收的移位寄存器（1924）存储，移位和输出来自A / D转换器（346）的数字数据（724）和用于计时移位寄存器的数据时钟（375）。该集成电路有五个信号通道，每个通道具有模拟放大和模数转换。通道可配置为输入信号放大，输入信号求和，模拟输出驱动和交流阻抗测量的各种组合。集成电路具有两条数字串行输入线和两条数字串行输出线，全部设计用于直接连接光耦合器。通道配置，增益和其他参数可通过串行数字输入信号进行外部控制。多达六个兼容的设备可以串连在一起。

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