专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明公开

EP3467832A1 MEMORY CONTROLLER AND METHOD FOR INTERLEAVING DRAM AND MRAM ACCESSES 有权
公开(公告)号：EP3467832A1
公开(公告)日：2019-04-10
申请号：EP18201610.5
申请日：2011-12-16
申请人： Everspin Technologies, Inc.
发明人： ALAM, Syed M. , ANDRE, Thomas , GOGL, Dietmar
IPC分类号： G11C7/10 , G11C8/04 , G11C11/4076 , G06F13/16
摘要： A memory controller and method for interleaving volatile and non-volatile memory different latencies and page sizes are described wherein a single DDR3 memory controller communicates with a number of memory modules comprising of at least non-volatile memory, e, g. spin torque magnetic random access memory, integrated in a different Rank or Channel with a volatile memory, e.g., dynamic random access memory (DRAM).

2. 发明授权

EP2656346B8 MEMORY ARRAY HAVING LOCAL SOURCE LINES 有权转让
公开(公告)号：EP2656346B8
公开(公告)日：2018-08-29
申请号：EP11850811.8
申请日：2011-12-20
申请人： Everspin Technologies, Inc.
发明人： ANDRE, Thomas
IPC分类号： G11C11/16
CPC分类号： G11C11/161 , G11C11/1659
摘要： A memory is provided that simplifies a fabrication process and structure by reducing the number of source lines and bitlines accessible to circuitry outside of the memory array. The memory has first and second row groups comprising a plurality of memory elements each coupled to one each of a plurality of M bit lines; first and second local source lines and first and second word lines, each coupled to each of the plurality of memory elements; and circuitry coupled to the first and second word lines and configured to select one of the first and second row groups, and coupled to the plurality of M bit lines and configured to apply current of magnitude N through the memory element in the selected row group coupled to one of the plurality of M bit lines by applying current of magnitude less than N to two or more of the remaining M-1 bit lines.

3. 发明公开

EP3188188A1 SELF-REFRENCE READ METHOD OF A SPIN TORQUE MAGNETIC RANDOM ACCESS MEMORY 有权转让
标题翻译：自旋转矩磁随机存取存储器的自折射读取方法
公开(公告)号：EP3188188A1
公开(公告)日：2017-07-05
申请号：EP17150776.7
申请日：2012-01-31
申请人： Everspin Technologies, Inc.
发明人： ALAM, Syed M. , ANDRE, Thomas , CROFT, Matthew R. , SUBRAMANIAN, Chitra , LIN, Halbert
IPC分类号： G11C11/00 , G11C11/16 , G11C29/04 , G11C13/00 , G06F11/10
CPC分类号： G11C11/1675 , G06F11/1048 , G06F11/1076 , G11C11/00 , G11C11/16 , G11C11/1673 , G11C11/1693 , G11C2013/0076 , G11C2029/0411
摘要： A spin-torque magnetoresistive memory comprises an array (602) of spin-torque magnetoresistive memory bits; a plurality of latches (626); array read circuits (610) coupled to the array of bits (602) and the plurality of latches (626), wherein the array read circuits are configured to:
sample bits in a page within the array of bits, wherein sampling provides a sampled voltage for each of the bits in the page, wherein the array read circuits are configured to sample each bit in the page by applying a first voltage across the bit and converting a current resulting from applying the first voltage to the sampled voltage;
after sampling the bits in the page, apply a first write current pulse to each of the bits in the page to set all of the bits in the page to a first logic state;
after applying the first write current pulse to each of the bits in the page, resample each of the bits in the page to provide a resampled voltage for each bit in the page, wherein the array read circuits are configured to resample each bit by reapplying the first voltage across the bit and adding an offset current to a current resulting from reapplying the first voltage across the bit, wherein the array read circuits are configured to generate the resampled voltage for each bit using the offset current and the current resulting from reapplying the first voltage across the bit;
for each bit in the page, compare the resampled voltage with the sampled voltage to determine a bit state for the bit, wherein the bit state for each bit is either the first logic state or a second logic state; and
store the bit state for each bit in the page in a corresponding latch of the plurality of latches (626). The memory comprises further array write circuits (612) coupled to the array of bits (602) and the plurality of latches (626), the array write circuits (612) configured to, for each of the bits in the page having the second logic state as stored in the plurality of latches (626), initiate a write-back to reset the bit to the second state in the array, wherein the write-back for each bit includes applying a second write current pulse to set the bit to the second state.
摘要翻译：自旋扭矩磁阻存储器包括自旋扭矩磁阻存储器位的阵列（602）多个锁存器（626）; 耦合到所述位阵列（602）和所述多个锁存器（626）的阵列读取电路（610），其中所述阵列读取电路被配置为：对所述位阵列内的页中的位进行采样，其中采样提供采样电压对于所述页面中的每个位，其中所述阵列读取电路被配置为通过在所述位上施加第一电压来采样所述页中的每个位，并且将通过将所述第一电压施加到所述采样电压而产生的电流转换; 在采样所述页面中的比特之后，向所述页面中的每个比特应用第一写入电流脉冲以将所述页面中的所有比特设置为第一逻辑状态; 在将所述第一写入电流脉冲施加到所述页面中的每个位之后，重新采样所述页面中的每个位以为所述页面中的每个位提供重新采样电压，其中所述阵列读取电路被配置为通过重新应用在所述位上施加第一电压并且将补偿电流添加到通过在所述位上重新施加所述第一电压而产生的电流，其中所述阵列读取电路被配置为使用所述补偿电流和通过重新应用所述第一电压位上的电压; 对于页中的每个位，比较重新采样电压和采样电压以确定该位的位状态，其中每个位的位状态是第一逻辑状态或第二逻辑状态; 并且将该页中每个比特的比特状态存储在多个锁存器（626）的相应锁存器中。存储器包括耦合到位阵列（602）和多个锁存器（626）的另外的阵列写入电路（612），阵列写入电路（612）被配置为对于具有第二逻辑的页面中的每个位状态存储在多个锁存器（626）中，启动回写以将该位复位到阵列中的第二状态，其中每个位的回写包括施加第二写入电流脉冲以将该位设置为第二状态。

4. 发明公开

EP3117433A1 NONVOLATILE LOGIC AND SECURITY CIRCUITS 审中-公开
标题翻译： NICHTFLÜCHTIGELOGIK- UND SICHERHEITSSCHALTUNGEN
公开(公告)号：EP3117433A1
公开(公告)日：2017-01-18
申请号：EP15761760.6
申请日：2015-03-10
申请人： Everspin Technologies, Inc.
发明人： ANDRE, Thomas
IPC分类号： G11C11/02
CPC分类号： G11C11/1673 , G06F11/1068 , G09C1/00 , G11C5/06 , G11C11/1659 , G11C11/1675 , G11C13/0002 , G11C13/0026 , G11C13/003 , G11C13/004 , G11C13/0069 , G11C14/0081 , G11C14/009 , G11C29/52 , G11C2213/75 , G11C2213/77 , H01L27/228 , H01L43/02 , H01L43/08 , H04L9/0866
摘要： In some examples, a nonvolatile storage element may be configured to store a state or value during a low power or powered down period of a circuit. For example, the nonvolatile storage element may include a bridge of resistive elements that have a resistive state that may be configured by applying voltages to multiple drive paths. A sense amplifier may be connected to the bridge in order to resolve a voltage differential associated with the bridge to ether power or ground and, thereby determine the state associated with on the nonvolatile storage element.
摘要翻译：在一些示例中，非易失性存储元件可以被配置为在电路的低功率或掉电时段期间存储状态或值。例如，非易失性存储元件可以包括具有电阻状态的电阻元件桥，可以通过向多个驱动路径施加电压来配置电阻状态。感测放大器可以连接到桥，以便将与桥接器相关联的电压差分解成以太网电力或接地，从而确定与非易失性存储元件相关联的状态。

5. 发明公开

EP2671229A1 METHOD OF WRITING TO A SPIN TORQUE MAGNETIC RANDOM ACCESS MEMORY 有权转让
标题翻译：方法写在一拧，扭矩磁直接访问存储器
公开(公告)号：EP2671229A1
公开(公告)日：2013-12-11
申请号：EP12742660.9
申请日：2012-01-31
申请人： Everspin Technologies, Inc.
发明人： ALAM, Syed M. , ANDRE, Thomas , CROFT, Matthew R. , SUBRAMANIAN, Chitra , LIN, Halbert
IPC分类号： G11C11/00
CPC分类号： G11C11/1675 , G06F11/1048 , G06F11/1076 , G11C11/00 , G11C11/16 , G11C11/1673 , G11C11/1693 , G11C2013/0076 , G11C2029/0411
摘要： A spin-torque magnetoresistive memory comprises an array (602) of spin-torque magnetoresistive memory bits; a plurality of latches (626); array read circuits (610) coupled to the array of bits (602) and the plurality of latches (626), wherein the array read circuits are configured to: sample bits in a page within the array of bits, wherein sampling provides a sampled voltage for each of the bits in the page, wherein the array read circuits are configured to sample each bit in the page by applying a first voltage across the bit and converting a current resulting from applying the first voltage to the sampled voltage; after sampling the bits in the page, apply a first write current pulse to each of the bits in the page to set all of the bits in the page to a first logic state; after applying the first write current pulse to each of the bits in the page, resample each of the bits in the page to provide a resampled voltage for each bit in the page, wherein the array read circuits are configured to resample each bit by reapplying the first voltage across the bit and adding an offset current to a current resulting from reapplying the first voltage across the bit, wherein the array read circuits are configured to generate the resampled voltage for each bit using the offset current and the current resulting from reapplying the first voltage across the bit; for each bit in the page, compare the resampled voltage with the sampled voltage to determine a bit state for the bit, wherein the bit state for each bit is either the first logic state or a second logic state; and store the bit state for each bit in the page in a corresponding latch of the plurality of latches (626). The memory comprises further array write circuits (612) coupled to the array of bits (602) and the plurality of latches (626), the array write circuits (612) configured to, for each of the bits in the page having the second logic state as stored in the plurality of latches (626), initiate a write-back to reset the bit to the second state in the array, wherein the write-back for each bit includes applying a second write current pulse to set the bit to the second state.

6. 发明公开

EP2652741A1 MEMORY CONTROLLER AND METHOD FOR INTERLEAVING DRAM AND MRAM ACCESSES 有权转让
标题翻译： SPEICHERSTEUERUNG UND VERFAHREN ZUR VERSCHACHTELTEL VON DRAM- UND MRAM-ZUGRIFFEN
公开(公告)号：EP2652741A1
公开(公告)日：2013-10-23
申请号：EP11847949.2
申请日：2011-12-16
申请人： Everspin Technologies, Inc.
发明人： ALAM, Syed M. , ANDRE, Thomas , GOGL, Dietmar
IPC分类号： G11C16/04
CPC分类号： G06F3/0659 , G06F3/0611 , G06F3/0685 , G06F12/0246 , G06F12/0638 , G06F13/1694 , G06F2212/205 , G06F2212/7201 , G11C7/1042 , G11C7/1072 , G11C8/04 , G11C11/005 , G11C11/16 , G11C11/1673 , G11C11/1675 , G11C11/4076 , G11C11/4091 , G11C11/4094 , G11C11/4096 , G11C14/0036
摘要： A memory controller and method for interleaving volatile and non-volatile memory different latencies and page sizes are described wherein a single DDR3 memory controller communicates with a number of memory modules comprising of at least non-volatile memory, e.g., spin torque magnetic random access memory, integrated in a different Rank or Channel with a volatile memory, e.g., dynamic random access memory (DRAM).
摘要翻译：描述了用于交错易失性和非易失性存储器的不同延迟和页面大小的存储器控制器和方法，其中单个DDR3存储器控制器与包括至少非易失性存储器的多个存储器模块进行通信，例如，自旋转矩磁性随机存取存储器，集成在具有易失性存储器的不同等级或信道中，例如动态随机存取存储器（DRAM）。

7. 发明授权

EP3201776B1 SHORT DETECTION AND INVERSION 有权转让
公开(公告)号：EP3201776B1
公开(公告)日：2020-07-29
申请号：EP15845671.5
申请日：2015-09-29
申请人： Everspin Technologies, Inc.
发明人： ANDRE, Thomas , SLAUGHTER, Jon , HOUSSAMEDDINE, Dimitri , ALAM, Syed M.
IPC分类号： G06F11/10

8. 发明授权

EP2671155B1 METHOD OF READING AND WRITING TO A SPIN TORQUE MAGNETIC RANDOM ACCESS MEMORY WITH ERROR CORRECTING CODE 有权转让
标题翻译：读取和写入具有错误校正码的自旋转矩磁随机存取存储器的方法
公开(公告)号：EP2671155B1
公开(公告)日：2017-10-11
申请号：EP12741764.0
申请日：2012-01-31
申请人： Everspin Technologies, Inc.
发明人： ALAM, Syed M. , ANDRE, Thomas , CROFT, Matthew R.
IPC分类号： G06F11/00 , G06F11/10
CPC分类号： G06F11/1076 , G06F11/1012 , G06F11/1048 , G11C11/1673 , G11C11/1675 , H03M13/2906

9. 发明公开

EP3201776A1 SHORT DETECTION AND INVERSION 有权转让
标题翻译：短探测和反演
公开(公告)号：EP3201776A1
公开(公告)日：2017-08-09
申请号：EP15845671.5
申请日：2015-09-29
申请人： Everspin Technologies, Inc.
发明人： ANDRE, Thomas , SLAUGHTER, Jon , HOUSSAMEDDINE, Dimitri , ALAM, Syed M.
IPC分类号： G06F11/10
摘要： In some examples, a memory device may be configured to store data in either an original or an inverted state based at least in part on a state associated with one or more shorted bit cells. For instance, the memory device may be configured to identify a shorted bit cell within a memory array and to store the data in the memory array, such that a state of the data bit stored in the shorted bit cell matches the state associated with the shorted bit cell.
摘要翻译：在一些实例中，存储器装置可经配置以至少部分基于与一个或一个以上短接位单元相关联的状态以原始或倒置状态存储数据。举例来说，存储器装置可经配置以识别存储器阵列内的短接位单元并将数据存储在存储器阵列中，使得存储在短接位单元中的数据位的状态匹配与短接位单元。

10. 发明公开

EP3117302A1 BURST LENGTH DEFINED PAGE SIZE 审中-公开
标题翻译： BURSTLÄNGENDEFINIERTESEITENGRÖSSE
公开(公告)号：EP3117302A1
公开(公告)日：2017-01-18
申请号：EP15762428.9
申请日：2015-03-09
申请人： Everspin Technologies, Inc.
发明人： ANDRE, Thomas , ALAM, Syed M.
IPC分类号： G06F9/34
CPC分类号： G11C11/1675 , G06F12/0806 , G06F12/0879 , G06F2212/62 , G11C7/1018 , G11C7/1045 , G11C7/12 , G11C7/22 , G11C11/16 , G11C11/1655 , G11C11/1657 , G11C11/1659 , G11C11/1673 , G11C11/1693 , G11C11/4091 , G11C11/4094 , G11C11/419 , G11C11/5607 , Y02D10/13
摘要： In a spin-torque magnetic random access memory (MRAM) that includes local source lines, auto-booting of the word line is used to reduce power consumption by reusing charge already present from driving a plurality of bit lines during writing operations. Auto-booting is accomplished by first driving the word line to a first word line voltage. After such driving, the word line isolated. Subsequent driving of the plurality of bit lines that are capacitively coupled to the word line causes the word line voltage to be increased to a level desired to allow sufficient current to flow through a selected memory cell to write information into the selected memory cell. Additional embodiments include the use of a supplemental voltage provider that is able to further boost or hold the isolated word line at the needed voltage level.
摘要翻译：在包括本地源极线的自旋扭矩磁随机存取存储器（MRAM）中，字线的自动引导用于通过在写入操作期间重新使用已经存在的驱动多个位线的电荷来节省功耗。通过首先将字线驱动到第一字线电压来实现自动启动。经过这样的驾驶，字线隔离。随后驱动电容耦合到字线的多个位线使得字线电压增加到所需的水平，以允许足够的电流流过选定的存储器单元以将信息写入所选存储单元。另外的实施例包括使用能够进一步升高或保持隔离字线处于所需电压电平的补充电压提供器。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式