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1. 发明授权

EP2671229B1 METHOD OF WRITING TO A SPIN TORQUE MAGNETIC RANDOM ACCESS MEMORY 有权转让
公开(公告)号：EP2671229B1
公开(公告)日：2019-10-09
申请号：EP12742660.9
申请日：2012-01-31
申请人： Everspin Technologies, Inc.
发明人： ALAM, Syed M. , ANDRE, Thomas , CROFT, Matthew R. , SUBRAMANIAN, Chitra , LIN, Halbert
IPC分类号： G11C11/00 , G11C11/16 , G11C29/04 , G11C13/00 , G06F11/10

2. 发明公开

EP3449483A1 DELAYED WRITE-BACK IN MEMORY 有权转让
公开(公告)号：EP3449483A1
公开(公告)日：2019-03-06
申请号：EP17704627.3
申请日：2017-01-30
申请人： Everspin Technologies, Inc.
发明人： ANDRE, Thomas , ALAM, Syed M. , SUBRAMANIAN, Chitra , BARKATULLAH, Javed S.
IPC分类号： G11C11/16 , G11C7/22 , G11C7/10 , G11C16/32

3. 发明公开

EP4184510A1 SYSTEM AND METHODS FOR DUAL STANDBY MODES IN MEMORY 审中-实审
公开(公告)号：EP4184510A1
公开(公告)日：2023-05-24
申请号：EP22204909.0
申请日：2022-11-01
申请人： Everspin Technologies, Inc.
发明人： ALAM, Syed M.
IPC分类号： G11C5/14 , G11C7/10 , G11C7/20 , G11C7/22 , G11C11/16 , G11C29/02 , G11C29/16 , G11C29/44
摘要： The present disclosure is drawn to, among other things, a method for accessing memory using dual standby modes, the method including receiving a first standby mode indication selecting a first standby mode from a first standby mode or a second standby mode, configuring a read bias system to provide a read bias voltage and a write bias system to provide approximately no voltage, or any voltage outside the necessary range for write operation, based on the first standby mode, receiving a second standby mode indication selecting the second standby mode, and configuring the read bias system to provide at least the read bias voltage and the write bias system to provide a write bias voltage based on the second standby mode, the read bias voltage being lower than the write bias voltage.

4. 发明公开

EP4083843A1 CRYPTOGRAPHIC MRAM AND METHODS THEREOF 审中-实审
公开(公告)号：EP4083843A1
公开(公告)日：2022-11-02
申请号：EP22169783.2
申请日：2022-04-25
申请人： Everspin Technologies, Inc.
发明人： ALAM, Syed M. , AGGARWAL, Sanjeev
IPC分类号： G06F21/86 , G06F7/58 , H04L9/08
摘要： The present disclosure is drawn to, among other things, a storage device. The storage device may include a magnetic tunnel junction (MTJ)-based storage array and a communication interface. The MTJ-based storage array may be configured to be damaged by a shorting voltage based on detection of a tamper event.

5. 发明公开

EP3467832A1 MEMORY CONTROLLER AND METHOD FOR INTERLEAVING DRAM AND MRAM ACCESSES 有权
公开(公告)号：EP3467832A1
公开(公告)日：2019-04-10
申请号：EP18201610.5
申请日：2011-12-16
申请人： Everspin Technologies, Inc.
发明人： ALAM, Syed M. , ANDRE, Thomas , GOGL, Dietmar
IPC分类号： G11C7/10 , G11C8/04 , G11C11/4076 , G06F13/16
摘要： A memory controller and method for interleaving volatile and non-volatile memory different latencies and page sizes are described wherein a single DDR3 memory controller communicates with a number of memory modules comprising of at least non-volatile memory, e, g. spin torque magnetic random access memory, integrated in a different Rank or Channel with a volatile memory, e.g., dynamic random access memory (DRAM).

6. 发明公开

EP3188188A1 SELF-REFRENCE READ METHOD OF A SPIN TORQUE MAGNETIC RANDOM ACCESS MEMORY 有权转让
标题翻译：自旋转矩磁随机存取存储器的自折射读取方法
公开(公告)号：EP3188188A1
公开(公告)日：2017-07-05
申请号：EP17150776.7
申请日：2012-01-31
申请人： Everspin Technologies, Inc.
发明人： ALAM, Syed M. , ANDRE, Thomas , CROFT, Matthew R. , SUBRAMANIAN, Chitra , LIN, Halbert
IPC分类号： G11C11/00 , G11C11/16 , G11C29/04 , G11C13/00 , G06F11/10
CPC分类号： G11C11/1675 , G06F11/1048 , G06F11/1076 , G11C11/00 , G11C11/16 , G11C11/1673 , G11C11/1693 , G11C2013/0076 , G11C2029/0411
摘要： A spin-torque magnetoresistive memory comprises an array (602) of spin-torque magnetoresistive memory bits; a plurality of latches (626); array read circuits (610) coupled to the array of bits (602) and the plurality of latches (626), wherein the array read circuits are configured to:
sample bits in a page within the array of bits, wherein sampling provides a sampled voltage for each of the bits in the page, wherein the array read circuits are configured to sample each bit in the page by applying a first voltage across the bit and converting a current resulting from applying the first voltage to the sampled voltage;
after sampling the bits in the page, apply a first write current pulse to each of the bits in the page to set all of the bits in the page to a first logic state;
after applying the first write current pulse to each of the bits in the page, resample each of the bits in the page to provide a resampled voltage for each bit in the page, wherein the array read circuits are configured to resample each bit by reapplying the first voltage across the bit and adding an offset current to a current resulting from reapplying the first voltage across the bit, wherein the array read circuits are configured to generate the resampled voltage for each bit using the offset current and the current resulting from reapplying the first voltage across the bit;
for each bit in the page, compare the resampled voltage with the sampled voltage to determine a bit state for the bit, wherein the bit state for each bit is either the first logic state or a second logic state; and
store the bit state for each bit in the page in a corresponding latch of the plurality of latches (626). The memory comprises further array write circuits (612) coupled to the array of bits (602) and the plurality of latches (626), the array write circuits (612) configured to, for each of the bits in the page having the second logic state as stored in the plurality of latches (626), initiate a write-back to reset the bit to the second state in the array, wherein the write-back for each bit includes applying a second write current pulse to set the bit to the second state.
摘要翻译：自旋扭矩磁阻存储器包括自旋扭矩磁阻存储器位的阵列（602）多个锁存器（626）; 耦合到所述位阵列（602）和所述多个锁存器（626）的阵列读取电路（610），其中所述阵列读取电路被配置为：对所述位阵列内的页中的位进行采样，其中采样提供采样电压对于所述页面中的每个位，其中所述阵列读取电路被配置为通过在所述位上施加第一电压来采样所述页中的每个位，并且将通过将所述第一电压施加到所述采样电压而产生的电流转换; 在采样所述页面中的比特之后，向所述页面中的每个比特应用第一写入电流脉冲以将所述页面中的所有比特设置为第一逻辑状态; 在将所述第一写入电流脉冲施加到所述页面中的每个位之后，重新采样所述页面中的每个位以为所述页面中的每个位提供重新采样电压，其中所述阵列读取电路被配置为通过重新应用在所述位上施加第一电压并且将补偿电流添加到通过在所述位上重新施加所述第一电压而产生的电流，其中所述阵列读取电路被配置为使用所述补偿电流和通过重新应用所述第一电压位上的电压; 对于页中的每个位，比较重新采样电压和采样电压以确定该位的位状态，其中每个位的位状态是第一逻辑状态或第二逻辑状态; 并且将该页中每个比特的比特状态存储在多个锁存器（626）的相应锁存器中。存储器包括耦合到位阵列（602）和多个锁存器（626）的另外的阵列写入电路（612），阵列写入电路（612）被配置为对于具有第二逻辑的页面中的每个位状态存储在多个锁存器（626）中，启动回写以将该位复位到阵列中的第二状态，其中每个位的回写包括施加第二写入电流脉冲以将该位设置为第二状态。

7. 发明公开

EP2671229A1 METHOD OF WRITING TO A SPIN TORQUE MAGNETIC RANDOM ACCESS MEMORY 有权转让
标题翻译：方法写在一拧，扭矩磁直接访问存储器
公开(公告)号：EP2671229A1
公开(公告)日：2013-12-11
申请号：EP12742660.9
申请日：2012-01-31
申请人： Everspin Technologies, Inc.
发明人： ALAM, Syed M. , ANDRE, Thomas , CROFT, Matthew R. , SUBRAMANIAN, Chitra , LIN, Halbert
IPC分类号： G11C11/00
CPC分类号： G11C11/1675 , G06F11/1048 , G06F11/1076 , G11C11/00 , G11C11/16 , G11C11/1673 , G11C11/1693 , G11C2013/0076 , G11C2029/0411
摘要： A spin-torque magnetoresistive memory comprises an array (602) of spin-torque magnetoresistive memory bits; a plurality of latches (626); array read circuits (610) coupled to the array of bits (602) and the plurality of latches (626), wherein the array read circuits are configured to: sample bits in a page within the array of bits, wherein sampling provides a sampled voltage for each of the bits in the page, wherein the array read circuits are configured to sample each bit in the page by applying a first voltage across the bit and converting a current resulting from applying the first voltage to the sampled voltage; after sampling the bits in the page, apply a first write current pulse to each of the bits in the page to set all of the bits in the page to a first logic state; after applying the first write current pulse to each of the bits in the page, resample each of the bits in the page to provide a resampled voltage for each bit in the page, wherein the array read circuits are configured to resample each bit by reapplying the first voltage across the bit and adding an offset current to a current resulting from reapplying the first voltage across the bit, wherein the array read circuits are configured to generate the resampled voltage for each bit using the offset current and the current resulting from reapplying the first voltage across the bit; for each bit in the page, compare the resampled voltage with the sampled voltage to determine a bit state for the bit, wherein the bit state for each bit is either the first logic state or a second logic state; and store the bit state for each bit in the page in a corresponding latch of the plurality of latches (626). The memory comprises further array write circuits (612) coupled to the array of bits (602) and the plurality of latches (626), the array write circuits (612) configured to, for each of the bits in the page having the second logic state as stored in the plurality of latches (626), initiate a write-back to reset the bit to the second state in the array, wherein the write-back for each bit includes applying a second write current pulse to set the bit to the second state.

8. 发明公开

EP2652741A1 MEMORY CONTROLLER AND METHOD FOR INTERLEAVING DRAM AND MRAM ACCESSES 有权转让
标题翻译： SPEICHERSTEUERUNG UND VERFAHREN ZUR VERSCHACHTELTEL VON DRAM- UND MRAM-ZUGRIFFEN
公开(公告)号：EP2652741A1
公开(公告)日：2013-10-23
申请号：EP11847949.2
申请日：2011-12-16
申请人： Everspin Technologies, Inc.
发明人： ALAM, Syed M. , ANDRE, Thomas , GOGL, Dietmar
IPC分类号： G11C16/04
CPC分类号： G06F3/0659 , G06F3/0611 , G06F3/0685 , G06F12/0246 , G06F12/0638 , G06F13/1694 , G06F2212/205 , G06F2212/7201 , G11C7/1042 , G11C7/1072 , G11C8/04 , G11C11/005 , G11C11/16 , G11C11/1673 , G11C11/1675 , G11C11/4076 , G11C11/4091 , G11C11/4094 , G11C11/4096 , G11C14/0036
摘要： A memory controller and method for interleaving volatile and non-volatile memory different latencies and page sizes are described wherein a single DDR3 memory controller communicates with a number of memory modules comprising of at least non-volatile memory, e.g., spin torque magnetic random access memory, integrated in a different Rank or Channel with a volatile memory, e.g., dynamic random access memory (DRAM).
摘要翻译：描述了用于交错易失性和非易失性存储器的不同延迟和页面大小的存储器控制器和方法，其中单个DDR3存储器控制器与包括至少非易失性存储器的多个存储器模块进行通信，例如，自旋转矩磁性随机存取存储器，集成在具有易失性存储器的不同等级或信道中，例如动态随机存取存储器（DRAM）。

9. 发明公开

EP4030430A2 MIDPOINT SENSING REFERENCE GENERATION FOR STT-MRAM 审中-实审
公开(公告)号：EP4030430A2
公开(公告)日：2022-07-20
申请号：EP21210921.9
申请日：2021-11-29
申请人： Everspin Technologies, Inc.
发明人： ALAM, Syed M. , ZHANG, Yaojun , NEUMEYER, Frederick
IPC分类号： G11C7/14 , G11C11/16
摘要： The present disclosure is drawn to a magnetoresistive device including an array of memory cells arranged in rows and columns, each memory cell comprising a magnetic tunnel junction, each row comprising a word line, and each column comprising a bit line; a column select device that selects a bit line. The magnetoresistive device also includes a sense amplifier comprising a first input corresponding to a selected bit line, a second input corresponding to a reference bit line, and a data output. The plurality of columns comprise a reference column, the reference column comprising a conductive element coupled to the magnetic tunnel junctions in the reference column.

10. 发明授权

EP3201776B1 SHORT DETECTION AND INVERSION 有权转让
公开(公告)号：EP3201776B1
公开(公告)日：2020-07-29
申请号：EP15845671.5
申请日：2015-09-29
申请人： Everspin Technologies, Inc.
发明人： ANDRE, Thomas , SLAUGHTER, Jon , HOUSSAMEDDINE, Dimitri , ALAM, Syed M.
IPC分类号： G06F11/10

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