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1. 发明公开

EP2575134A3 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：EP2575134A3
公开(公告)日：2013-07-03
申请号：EP12186309.6
申请日：2012-09-27
申请人： Elpida Memory, Inc.
发明人： Shido, Taihei , Dono, Chiaki , Kondo, Chikara , Miyazaki, Shinya
IPC分类号： G11C7/10 , G11C11/4096 , G06F12/00
CPC分类号： G06F12/00 , G11C7/1006 , G11C7/1012 , G11C7/1027 , G11C11/4096
摘要： Disclosed herein is a device that a device including first data lines transmitting a plurality of sequential first data bits, respectively, second data lines transmitting a plurality of sequential second data bits, respectively, third data lines transmitting a plurality of sequential third data bits, respectively, a BOC circuit rearranging order of the plurality of first data bits supplied from the plurality of first data lines in accordance with address information, the BOC circuit supplying the resultant to the plurality of second data lines as the plurality of second data bits, and a DBI circuit performing inversion or non-inversion of the plurality of second data bits supplied from the plurality of second data lines independently of each other in accordance with a predetermined condition, the DBI circuit supplying the resultant to the plurality of third data lines as the plurality of third data bits.
摘要翻译：本文公开了一种设备，该设备包括分别发送多个连续的第一数据比特的第一数据线，分别发送多个连续的第二数据比特的第二数据线和分别发送多个连续的第三数据比特的第三数据线的设备 BOC电路根据地址信息重新排列从多条第一数据线提供的多个第一数据位的顺序，BOC电路将结果提供给多条第二数据线作为多个第二数据位，以及a DBI电路根据预定条件彼此独立地对从多个第二数据线提供的多个第二数据位进行反相或非反转，DBI电路将结果作为多个第三数据线提供给多个的第三数据位。

2. 发明公开

EP2575134A2 Semiconductor device 有权
标题翻译： Halbleiterbauelement
公开(公告)号：EP2575134A2
公开(公告)日：2013-04-03
申请号：EP12186309.6
申请日：2012-09-27
申请人： Elpida Memory, Inc.
发明人： Shido, Taihei , Dono, Chiaki , Kondo, Chikara , Miyazaki, Shinya
IPC分类号： G11C7/10 , G11C11/4096
CPC分类号： G06F12/00 , G11C7/1006 , G11C7/1012 , G11C7/1027 , G11C11/4096
摘要： Disclosed herein is a device that a device including first data lines transmitting a plurality of sequential first data bits, respectively, second data lines transmitting a plurality of sequential second data bits, respectively, third data lines transmitting a plurality of sequential third data bits, respectively, a BOC circuit rearranging order of the plurality of first data bits supplied from the plurality of first data lines in accordance with address information, the BOC circuit supplying the resultant to the plurality of second data lines as the plurality of second data bits, and a DBI circuit performing inversion or non-inversion of the plurality of second data bits supplied from the plurality of second data lines independently of each other in accordance with a predetermined condition, the DBI circuit supplying the resultant to the plurality of third data lines as the plurality of third data bits.
摘要翻译：本文公开了一种装置，其包括分别包括多个顺序的第一数据位的第一数据线和分别发送多个连续的第二数据位的第二数据线的第三数据线分别发送多个连续的第三数据位的装置根据地址信息从多个第一数据线提供的多个第一数据位重排排列顺序的BOC电路，将所得结果作为多个第二数据位提供给多个第二数据线的BOC电路，以及 DBI电路根据预定条件独立地执行从多个第二数据线提供的多个第二数据位的反转或非反转，DBI电路将结果提供给多个第三数据线作为多个的第三个数据位。

3. 发明公开

EP2575137A3 Semiconductor device 有权转让
公开(公告)号：EP2575137A3
公开(公告)日：2013-05-15
申请号：EP12186212.2
申请日：2012-09-27
申请人： Elpida Memory, Inc.
发明人： Kondo, Chikara
IPC分类号： G11C11/4076 , G11C11/408 , G11C11/4096 , G11C7/22 , G11C7/10 , G11C11/4072
CPC分类号： G11C11/4093 , G06F13/161 , G11C7/1045 , G11C7/109 , G11C7/1093 , G11C7/222 , G11C11/4063 , G11C11/4072 , G11C11/4076 , G11C11/4087 , G11C11/4096 , Y02D10/14
摘要： Disclosed herein is a semiconductor device that includes a command decoder activating a first mode register setting signal in response to a mode register setting command supplied from outside, a first latency shifter activating a second mode register setting signal after elapse of predetermined cycles of a clock signal since the first mode register setting signal is activated, and a mode register storing a mode signal supplied from outside in response to the second mode register setting signal.

4. 发明授权

EP2575134B1 Semiconductor device 有权
公开(公告)号：EP2575134B1
公开(公告)日：2014-06-18
申请号：EP12186309.6
申请日：2012-09-27
申请人： Elpida Memory, Inc.
发明人： Shido, Taihei , Dono, Chiaki , Kondo, Chikara , Miyazaki, Shinya
IPC分类号： G11C7/10 , G11C11/4096 , G06F12/00
CPC分类号： G06F12/00 , G11C7/1006 , G11C7/1012 , G11C7/1027 , G11C11/4096

5. 发明公开

EP2575137A2 Semiconductor device 有权转让
标题翻译：半导体器件
公开(公告)号：EP2575137A2
公开(公告)日：2013-04-03
申请号：EP12186212.2
申请日：2012-09-27
申请人： Elpida Memory, Inc.
发明人： Kondo, Chikara
IPC分类号： G11C11/4076 , G11C11/408 , G11C11/4096 , G11C7/22 , G11C7/10
CPC分类号： G11C11/4093 , G06F13/161 , G11C7/1045 , G11C7/109 , G11C7/1093 , G11C7/222 , G11C11/4063 , G11C11/4072 , G11C11/4076 , G11C11/4087 , G11C11/4096 , Y02D10/14
摘要： Disclosed herein is a semiconductor device that includes a command decoder activating a first mode register setting signal in response to a mode register setting command supplied from outside, a first latency shifter activating a second mode register setting signal after elapse of predetermined cycles of a clock signal since the first mode register setting signal is activated, and a mode register storing a mode signal supplied from outside in response to the second mode register setting signal.
摘要翻译：本发明公开了一种半导体器件，其包括响应于从外部提供的模式寄存器设置命令而激活第一模式寄存器设置信号的命令解码器，第一等待时间移位器在时钟信号的预定周期过去之后激活第二模式寄存器设置信号由于第一模式寄存器设置信号被激活，并且模式寄存器存储响应于第二模式寄存器设置信号从外部提供的模式信号。

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