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1. 发明公开

EP0674392A1 Phase locked loop 无效
标题翻译：锁相环
公开(公告)号：EP0674392A1
公开(公告)日：1995-09-27
申请号：EP95301251.5
申请日：1995-02-27
申请人： DISCOVISION ASSOCIATES
发明人： Jones, Anthony Mark
IPC分类号： H03L7/089
CPC分类号： H03L7/0891 , Y10S331/02
摘要： An improved phase locked loop utilizing control logic generated by a phase detector to eliminate sensitivity to uncorrelated noise when the loop is in lock. The phase locked loop comprises a differential filter (117) having first and second input lines. A logic element (115) is responsive to the locked state of the phase locked loop for connecting said first and second input lines together whereby uncorrelated noise is common-mode to the filter and, as such, does not affect the VCO (121) input.
The phase locked loop is particularly useful in clock signal synthesis and in an IC used to display video signals.
摘要翻译：一种改进的锁相环，利用相位检测器产生的控制逻辑消除环路锁定时对不相关噪声的敏感性。锁相环包括具有第一和第二输入线的差分滤波器（117）。逻辑元件（115）响应于锁相环的锁定状态，用于将所述第一和第二输入线连接在一起，由此不相关噪声是滤波器的共模，并且因此不影响VCO（121）输入。锁相环在时钟信号合成和用于显示视频信号的IC中特别有用。

2. 发明公开

EP0674388A1 Scannable latch and method of using the same 失效
标题翻译： Abtastbare Verriegelungschaltung和Verwendungsmethode derselben。
公开(公告)号：EP0674388A1
公开(公告)日：1995-09-27
申请号：EP95301252.3
申请日：1995-02-27
申请人： DISCOVISION ASSOCIATES
发明人： Jones, Anthony Mark , Davison, Michael Paul
IPC分类号： H03K3/037
CPC分类号： H03K3/356156 , H03K3/0375
摘要： A novel design for a fully static, see-through-latch with buffering is disclosed, which is capable of being configured to act as either a see-through-latch, a flip-flop as an aid to a test scan which will allow data to be scanned in and out of the latches, and an alternative flip-flop as an aid to testing intervening combinatorial logic.
摘要翻译：公开了一种用于具有缓冲的完全静态，直通式锁存器的新颖设计，其能够被配置为充当通过触发器，触发器，以帮助测试扫描，这将允许数据被扫描进入和离开锁存器，以及另一种触发器，以辅助测试中间组合逻辑。

3. 发明公开

EP0674266A3 Method and apparatus for interfacing with ram 失效
标题翻译：用于与RAM存储器接口的方法和装置。
公开(公告)号：EP0674266A3
公开(公告)日：1997-12-03
申请号：EP95301272.1
申请日：1995-02-28
申请人： DISCOVISION ASSOCIATES
发明人： Jones, Anthony Mark , Robbins, William Philip , Patterson, Donald William Walker , Wise, Adrian Philip , Finch, Helen Rosemary , Sotheran, Martin William
IPC分类号： G06F12/02
CPC分类号： G06F13/1689 , G06F12/0207 , G06F12/04 , G06F12/0607 , G06F13/1673 , G06F13/28 , H04N19/13 , H04N19/42 , H04N19/423 , H04N19/61 , H04N19/91
摘要： The present invention is directed to a number of techniques for addressing and accessing memory, including accessing from RAM a number M of words that is less than the predetermined fixed burst length N of the RAM. Also disclosed is a method for accessing Dynamic Random Access Memory (DRAM) to store and retrieve data words associated with a two dimensional image, and a procedure for providing a word with fixed width, having a fixed number of bits to be used for addressing variable width data, and having a width defining field and address field, is disclosed. There is also disclosed a method to control the buffering of encoded video data organized as frames or fields. This method involves determining the picture number of each incoming decoded frame, determining the expected presentation number at any time and marking any buffer as ready when its picture number is on or after the presentation number. Finally, there is disclosed a RAM interface for connecting a bus to RAM wherein a separate address generator generates the addresses the RAM interface needs to address the RAM. The address generator communicates with the RAM interface via a two wire interface.

4. 发明授权

EP1026600B1 Method and apparatus for interfacing with RAM 失效
标题翻译：用于与RAM存储器接口的方法和装置
公开(公告)号：EP1026600B1
公开(公告)日：2004-10-06
申请号：EP00201754.9
申请日：1995-02-28
申请人： Discovision Associates
发明人： Jones, Anthony Mark , Robbins, William Philip , Patterson, Donald William Walker , Wise, Adrian Philip , Finch, Helen Rosemary , Sotheran, Martin William
IPC分类号： G06F13/42 , G11C7/00 , G06F12/02 , G06F13/16
CPC分类号： G06F13/1689 , G06F12/0207 , G06F12/04 , G06F12/0607 , G06F13/1673 , G06F13/28 , H04N19/13 , H04N19/42 , H04N19/423 , H04N19/61 , H04N19/91

5. 发明公开

EP0871133A1 Method and arrangement for transformation of signals from a frequency to a time domain 失效
标题翻译：用于信号在时域中的转变从一个频率范围内的方法和装置
公开(公告)号：EP0871133A1
公开(公告)日：1998-10-14
申请号：EP98201876.4
申请日：1992-06-26
申请人： Discovision Associates
发明人： Jones, Anthony Mark , Dewar, Kevin Douglas , Sotheran, Martin William
IPC分类号： G06F17/14
CPC分类号： G06F17/147
摘要： A system for transforming digital signals from a frequency to a time representation, in which the digital signals are arranged in groups of N data input words, comprising :

means for forcing predetermined bits of selected internal data words in the system to predetermined binary values, whereby the statistical accuracy of the system is improved relative to a predetermined test input data set,
pre-common processing means (PREC) arranged to perform predetermined pairing operations on odd-numbered ones of the input words and to transmit even-numbered ones of the input words to pre-common outputs ; and
post-common processing means (POSTC) arranged to perform predetermined output scaling operations on the odd common processing means output values to form post-processed odd values and to arithmetically combine the post-processed odd values with the even common processing means output values to generate high- and low-order output words.
The system is arranged such that the output words contain inverse discrete cosine transformation values corresponding to the input data words.
摘要翻译：一种用于从频率变换数字信号，以时间表示，其中，所述数字信号在的N个数据输入字的组排列的系统，包括：用于迫使选择的内部数据字的预定位在系统中预定的二进制值，由此该系统的统计精确度相对于预定测试输入数据集被改善，预共用处理手段（PREC）布置成在输入字奇数号的执行预定的配对操作和传输输入的偶数的字预共用输出; 布置成在奇数公共处理执行预定的输出缩放操作和后公共处理装置（POSTC）装置输出值来塑造后处理奇值，并用算术与偶数公共处理结合经后处理的奇值的装置的输出值产生高和低阶输出字。该系统被安排检查并输出字包含逆离散余弦变换值对应于输入数据字。

6. 发明公开

EP0674266A2 Method and apparatus for interfacing with ram 失效
标题翻译： Verfahren und Vorrichtung zur Schnittstellenbildung mit RAM-Speicher。
公开(公告)号：EP0674266A2
公开(公告)日：1995-09-27
申请号：EP95301272.1
申请日：1995-02-28
申请人： DISCOVISION ASSOCIATES
发明人： Jones, Anthony Mark , Robbins, William Philip , Patterson, Donald William Walker , Wise, Adrian Philip , Finch, Helen Rosemary , Sotheran, Martin William
IPC分类号： G06F12/02
CPC分类号： G06F13/1689 , G06F12/0207 , G06F12/04 , G06F12/0607 , G06F13/1673 , G06F13/28 , H04N19/13 , H04N19/42 , H04N19/423 , H04N19/61 , H04N19/91
摘要： The present invention is directed to a number of techniques for addressing and accessing memory, including accessing from RAM a number M of words that is less than the predetermined fixed burst length N of the RAM. Also disclosed is a method for accessing Dynamic Random Access Memory (DRAM) to store and retrieve data words associated with a two dimensional image, and a procedure for providing a word with fixed width, having a fixed number of bits to be used for addressing variable width data, and having a width defining field and address field, is disclosed. There is also disclosed a method to control the buffering of encoded video data organized as frames or fields. This method involves determining the picture number of each incoming decoded frame, determining the expected presentation number at any time and marking any buffer as ready when its picture number is on or after the presentation number. Finally, there is disclosed a RAM interface for connecting a bus to RAM wherein a separate address generator generates the addresses the RAM interface needs to address the RAM. The address generator communicates with the RAM interface via a two wire interface.
摘要翻译：本发明涉及用于寻址和访问存储器的多种技术，包括从RAM访问小于RAM的预定固定突发长度N的M个字。还公开了一种用于访问动态随机存取存储器（DRAM）以存储和检索与二维图像相关联的数据字的方法，以及用于提供具有固定宽度的字，具有用于寻址变量的固定位数的过程宽度数据，并具有宽度定义字段和地址字段。还公开了一种控制被组织为帧或场的编码视频数据的缓冲的方法。该方法包括确定每个输入的解码帧的图像号码，在任何时间确定预期的呈现号码，并且当其图像号码在演示号码之后或之后将任何缓冲区标记为准备就绪。最后，公开了一种用于将总线连接到RAM的RAM接口，其中单独的地址发生器产生RAM接口需要寻址RAM的地址。地址生成器通过两线接口与RAM接口通信。

7. 发明公开

EP0575675A1 Method and arrangement for transformation of signals from a frequency to a time domaine 失效
标题翻译：一种用于信号在时域中的转变从一个频率范围内的方法和应用。
公开(公告)号：EP0575675A1
公开(公告)日：1993-12-29
申请号：EP92305927.3
申请日：1992-06-26
申请人： DISCOVISION ASSOCIATES
发明人： Jones, Anthony Mark , Dewar, Kevin Douglas , Sotheran, Martin William
IPC分类号： G06F15/332
CPC分类号： G06F17/147
摘要： An IDCT method decimates a 2-D IDCT into two 1-D IDCT operations and then operates separately on the even and odd pixel input words. In a common processing step, selected input values are passed directly to output adders and subtractors, while others are multiplied by constant, scaled cosine values. In a pre-common processing step, the lowest-order odd input word is pre-multiplied by √2, and the odd input words are summed pairwise before processing in a common processing step. In a post-common processing step, intermediate values corresponding to the processed odd input words are multiplied by predetermined coefficients to form odd resultant values. After calculation of the even and odd resultant values, the high-order and low-order outputs are formed by simple subtraction/addition, respectively, of the odd resultant values from/with the even resultant values. The input values are preferably scaled upward by a factor of √2. Selected bits of some intermediate resulting data words are optionally adjusted by forcing these bits to either "1" or "0".
The IDCT system includes a pre-common processing circuit (PREC), a common processing circuit (CBLK), and a post-common processing circuit (POSTC), which perform the necessary operations in the respective steps. The system also includes a controller (CNTL) to generate signals to control the loading of system latches and, preferably, to time-multiplex the application of the even and odd input words to latches in the pre-common circuit.
摘要翻译：的IDCT方法抽取的2-D IDCT成两个1-D IDCT操作，然后分别作用在偶数与奇数像素输入字。在一个共同的处理步骤中，选择的输入值被直接传递给输出加法器和减法器，而另一些则-乘以常数，缩放余弦值。在预共用处理步骤中，最低阶奇数输入字是2ROOT 2预相乘，并且奇输入字在共同处理步骤求和成对处理之前。在后共用处理步骤中，对应于处理奇输入字的中间值，乘以预定系数，以形成奇结果值。偶数和奇结果值的计算后，将高阶和低阶输出由简单的减法/加法分别从/与偶数结果值形成，奇结果值。输入值优选通过2. 2ROOT所选的一些中间所得数据字中的位的因子缩放的向上任选通过迫使论文位可以是“1”或“0”调整。该IDCT系统包括一个预共用处理电路（PREC），公共处理电路（CBLK），和一个后公共处理电路（POSTC），它们执行在respectivement步骤的必要的操作。因此，该系统包括控制器（CNTL）来生成信号，以控制系统的锁存器的加载和，优选地，向的偶数和奇数输入字的应用时间多路复用，来闩锁在预公共电路。

8. 发明公开

EP1026600A3 Method and apparatus for interfacing with RAM 失效
标题翻译：与RAM连接的方法和设备
公开(公告)号：EP1026600A3
公开(公告)日：2000-11-08
申请号：EP00201754.9
申请日：1995-02-28
申请人： Discovision Associates
发明人： Jones, Anthony Mark , Robbins, William Philip , Patterson, Donald William Walker , Wise, Adrian Philip , Finch, Helen Rosemary , Sotheran, Martin William
IPC分类号： G06F13/42 , G11C7/00 , G06F12/02 , G06F13/16
CPC分类号： G06F13/1689 , G06F12/0207 , G06F12/04 , G06F12/0607 , G06F13/1673 , G06F13/28 , H04N19/13 , H04N19/42 , H04N19/423 , H04N19/61 , H04N19/91
摘要： A RAM access system comprising: a RAM responsive to low level commands; a state machine generating a string of low level commands in response to a received high level command, the state machine having modes, wherein the string of low level commands generated in response to the high level command received in one mode differs from the string of low level commands generated in response to the high level command received in another mode.
摘要翻译：一种RAM存取系统，包括：响应于低电平命令的RAM; 状态机响应于接收到的高电平命令产生低电平命令串，所述状态机具有多个模式，其中响应于在一个模式中接收到的高电平命令而产生的低电平命令串不同于低串响应于在另一模式下接收到的高级命令而生成的级命令。

9. 发明公开

EP1026600A2 Method and apparatus for interfacing with RAM 失效
标题翻译：用于与RAM存储器接口的方法和装置
公开(公告)号：EP1026600A2
公开(公告)日：2000-08-09
申请号：EP00201754.9
申请日：1995-02-28
申请人： Discovision Associates
发明人： Jones, Anthony Mark , Robbins, William Philip , Patterson, Donald William Walker , Wise, Adrian Philip , Finch, Helen Rosemary , Sotheran, Martin William
IPC分类号： G06F13/42 , G11C7/00 , G06F12/02
CPC分类号： G06F13/1689 , G06F12/0207 , G06F12/04 , G06F12/0607 , G06F13/1673 , G06F13/28 , H04N19/13 , H04N19/42 , H04N19/423 , H04N19/61 , H04N19/91
摘要： A RAM access system comprising:

a RAM responsive to low level commands;
a state machine generating a string of low level commands in response to a received high level command, the state machine having modes, wherein the string of low level commands generated in response to the high level command received in one mode differs from the string of low level commands generated in response to the high level command received in another mode.

10. 发明授权

EP0674392B1 Phase locked loop 无效
公开(公告)号：EP0674392B1
公开(公告)日：1999-08-25
申请号：EP95301251.5
申请日：1995-02-27
申请人： DISCOVISION ASSOCIATES
发明人： Jones, Anthony Mark
IPC分类号： H03L7/089
CPC分类号： H03L7/0891 , Y10S331/02

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