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1. 发明授权

EP0464708B1 High speed bus system 失效
标题翻译：高速总线系统
公开(公告)号：EP0464708B1
公开(公告)日：1998-06-10
申请号：EP91110755.5
申请日：1991-06-28
申请人： DIGITAL EQUIPMENT CORPORATION
发明人： Ramanujan, Ray , Keller, James B. , Samaras, William A. , DeRosa, John , Stewart, Robert E.
IPC分类号： G06F15/16 , G06F13/36
CPC分类号： G06F15/173 , G06F15/167

2. 发明公开

EP0094178A3 Interface for serial data communications link 失效
标题翻译：串行数据通信接口LINK
公开(公告)号：EP0094178A3
公开(公告)日：1985-04-03
申请号：EP83302412
申请日：1983-04-28
申请人： DIGITAL EQUIPMENT CORPORATION
发明人： Stewart, Robert E. , Buzynski, John E. , Giggi, Robert
IPC分类号： H04L25/49 , H04L07/04 , H04L25/45 , G06F03/04
CPC分类号： H04L25/45 , G06F13/4213 , G06F13/423 , H04L7/042 , H04L25/4904
摘要： An interface circuit (10) for coupling a parallel data device (12) to a serial data channel (14,16) over which Manchester-type codes are transmitted. In the interface circuit, an efficient and reliable Manchester decoder (22), comprising a flip-flop (50), an exclusive-ore gate (52), and at least one delay line (58A or 588) separates the data and clocking signals. The serial data signals are clocked into a serial register (30) under control of the external clocking signals from the channel. A carrier detector (24) enables the serial register only when valid information signals are present. A parallel data register (40) receives in parallel the data from the serial data register. To get in phase the external clocking signals with the internal clock source, an internal clock synchronizing circuit (34, 42) recycles the internal clock source upon the occurrence of a synchronizing character that is transmitted over the serial data channel. In this fashion, the internal operations of the parallel data transfers are in phase, but isolated from the external clocking signals so that in the event that the external clocking signals become corrupted due to noise or simultaneous transmissions of information signals by different devices, the internal parallel transfer operations may continue freely without disruption.

3. 发明公开

EP0094177A3 Method and apparatus for direct memory-to-memory intercomputer communication 失效
标题翻译：用于直接存储器到存储器间通信通信的方法和装置
公开(公告)号：EP0094177A3
公开(公告)日：1985-01-09
申请号：EP83302411
申请日：1983-04-28
申请人： DIGITAL EQUIPMENT CORPORATION
发明人： Strecker, William D. , Stewart, Robert E. , Fuller, Samuel
IPC分类号： G06F15/16
CPC分类号： G06F15/167 , G06F15/177
摘要： Method and apparatus for transfer of packet-type information from the memory (24B) of one node (14) in a computer network to the memory (24C) of another node (16) in the network. The invention is of particular utility in transfers over serial buses (e.g., 18). Packets are sent from a named memory buffer (25A) at a first node (14) to a named memory buffer (25C) at a second node (16), allowing random access by the first node to the memory of the second node without either node having to have knowledge of the memory structure of the other; the source and destination buffer names are contained right in the transmitted packet. The first node (14) can both write to and read from the second node (16). An opcode (40A) sent in each packet signifies whether a read or write operation is to be performed. For reading from the second node, the opcode actually causes the second node to write back to the first node; in this situation, the second node to write back to the first node; in this situation, che second node, upon detecting the appropriate opcode, places the remainder of the received packet on a command queue (202), to be excuted with the commands locally generated at the second node, without need for host interruption.

4. 发明公开

EP0094178A2 Interface for serial data communications link 失效
标题翻译：接口，用于串行数据传输线。
公开(公告)号：EP0094178A2
公开(公告)日：1983-11-16
申请号：EP83302412.8
申请日：1983-04-28
申请人： DIGITAL EQUIPMENT CORPORATION
发明人： Stewart, Robert E. , Buzynski, John E. , Giggi, Robert
IPC分类号： H04L25/49 , H04L7/04 , H04L25/45 , G06F3/04
CPC分类号： H04L25/45 , G06F13/4213 , G06F13/423 , H04L7/042 , H04L25/4904
摘要： An interface circuit (10) for coupling a parallel data device (12) to a serial data channel (14,16) over which Manchester-type codes are transmitted. In the interface circuit, an efficient and reliable Manchester decoder (22), comprising a flip-flop (50), an exclusive-ore gate (52), and at least one delay line (58A or 588) separates the data and clocking signals. The serial data signals are clocked into a serial register (30) under control of the external clocking signals from the channel. A carrier detector (24) enables the serial register only when valid information signals are present. A parallel data register (40) receives in parallel the data from the serial data register. To get in phase the external clocking signals with the internal clock source, an internal clock synchronizing circuit (34, 42) recycles the internal clock source upon the occurrence of a synchronizing character that is transmitted over the serial data channel. In this fashion, the internal operations of the parallel data transfers are in phase, but isolated from the external clocking signals so that in the event that the external clocking signals become corrupted due to noise or simultaneous transmissions of information signals by different devices, the internal parallel transfer operations may continue freely without disruption.

5. 发明公开

EP0094177A2 Apparatus for direct memory-to-memory intercomputer communication 失效
标题翻译： Gerätzur direkten Speicher-zu-Speicherübertragungzwischen Rechnern。
公开(公告)号：EP0094177A2
公开(公告)日：1983-11-16
申请号：EP83302411.0
申请日：1983-04-28
申请人： DIGITAL EQUIPMENT CORPORATION
发明人： Strecker, William D. , Stewart, Robert E. , Fuller, Samuel
IPC分类号： G06F15/16
CPC分类号： G06F15/167 , G06F15/177
摘要： Method and apparatus for transfer of packet-type information from the memory (24B) of one node (14) in a computer network to the memory (24C) of another node (16) in the network. The invention is of particular utility in transfers over serial buses (e.g., 18). Packets are sent from a named memory buffer (25A) at a first node (14) to a named memory buffer (25C) at a second node (16), allowing random access by the first node to the memory of the second node without either node having to have knowledge of the memory structure of the other; the source and destination buffer names are contained right in the transmitted packet.
The first node (14) can both write to and read from the second node (16). An opcode (40A) sent in each packet signifies whether a read or write operation is to be performed. For reading from the second node, the opcode actually causes the second node to write back to the first node; in this situation, the second node to write back to the first node; in this situation, che second node, upon detecting the appropriate opcode, places the remainder of the received packet on a command queue (202), to be excuted with the commands locally generated at the second node, without need for host interruption.
摘要翻译：将分组类型信息从计算机网络中的一个节点（14）的存储器（24B）传送到网络中另一个节点（16）的存储器（24C）的方法和装置。本发明在通过串行总线（例如，18）的传输中特别有用。分组在第一节点（14）处从命名的存储器缓冲器（25A）发送到第二节点（16）处的命名存储器缓冲器（25C），允许第一节点随机访问第二节点的存储器，而无需任何节点必须知道另一个的存储器结构; 源和目标缓冲区名称直接包含在传输的数据包中。第一节点（14）可以向第二节点（16）写入和读取。在每个分组中发送的操作码（40A）表示是否执行读或写操作。为了从第二节点读取，操作码实际上使第二节点回写到第一节点; 在这种情况下，第二个节点要回写到第一个节点; 在这种情况下，第二节点在检测到适当的操作码时，将接收到的分组的剩余部分置于命令队列（202）上，以便在第二节点处本地生成的命令被排除，而不需要主机中断。

6. 发明公开

EP0486072A2 Interface for serial data communications link 失效
标题翻译： SchnittstellefürserielleDatenübertragungsleitung。
公开(公告)号：EP0486072A2
公开(公告)日：1992-05-20
申请号：EP91121094.6
申请日：1983-04-28
申请人： DIGITAL EQUIPMENT CORPORATION
发明人： Stewart, Robert E. , Buzynski, John E. , Giggi, Robert
IPC分类号： H04L25/49 , H04L25/45 , H04L7/04 , G06F13/42
CPC分类号： H04L25/45 , G06F13/4213 , G06F13/423 , H04L7/042 , H04L25/4904
摘要： An interface circuit (10) for coupling a parallel data device (12) to a serial data channel (14, 16) over which Manchester-type codes are transmitted. In the interface circuit, an efficient and reliable Manchester decoder (22), comprising a flip-flop (50), an exclusive-or gate (52), and at least one delay line (58A or 58B) separates the data and clocking signals. The serial data signals are clocked into a serial register (30) under control of the external clocking signals from the channel. A carrier detector (24) enables the serial register only when valid information signals are present. A parallel data register (40) receives in parallel the data from the serial data register. To get in phase the external clocking signals with the internal clock source, an internal clock synchronizing circuit (34, 42) recycles the internal clock source upon the occurrence of a synchronizing character that is transmitted over the serial data channel. In this fashion, the internal operations of the parallel data transfers are in phase, but isolated from the external clocking signals so that in the event that the external clocking signals become corrupted due to noise or simultaneous transmissions of information signals by different devices, the internal parallel transfer operations may continue freely without disruption.
摘要翻译：一种用于将并行数据装置（12）耦合到传输曼彻斯特型码的串行数据信道（14,16）的接口电路（10）。在接口电路中，包括触发器（50），异或门（52）和至少一个延迟线（58A或58B）的有效且可靠的曼彻斯特解码器（22）将数据和时钟信号。在来自信道的外部时钟信号的控制下，串行数据信号被计时到串行寄存器（30）。只有存在有效信息信号时，载波检测器（24）才能使能串行寄存器。并行数据寄存器（40）并行接收来自串行数据寄存器的数据。为了与内部时钟源同步外部时钟信号，内部时钟同步电路（34,42）在出现通过串行数据通道发送的同步字符时，再循环内部时钟源。以这种方式，并行数据传输的内部操作是同步的，但是与外部时钟信号隔离，使得在外部时钟信号由于不同设备的信号信号的噪声或同时传输而被破坏的情况下，内部并行传输操作可以自由继续而不中断。

7. 发明公开

EP0464708A1 High speed bus system 失效
标题翻译： Hochgeschwindigkeitsbussystem。
公开(公告)号：EP0464708A1
公开(公告)日：1992-01-08
申请号：EP91110755.5
申请日：1991-06-28
申请人： DIGITAL EQUIPMENT CORPORATION
发明人： Ramanujan, Ray , Keller, James B. , Samaras, William A. , DeRosa, John , Stewart, Robert E.
IPC分类号： G06F15/16 , G06F13/36
CPC分类号： G06F15/173 , G06F15/167
摘要： A high speed bus system for use in a shared memory system that allows for the high speed transmissions of commands and data between a number of processors and a memory array of a multi-processor, shared memory system, with the high speed bus system including a central unit and a series of uni-directional buses that connect between the plurality of processors and shared memory, with the central unit including arbitration logic and a series of multiplexers to determine which CPUs are granted access to shared buses, scheduling logic that works with the arbitration logic and multiplexers to determine which CPUs are granted access to the shared buses, and port logic for combining the CPU transmissions and determining if such transmissions are valid.
摘要翻译：一种在共享存储器系统中使用的高速总线系统，其允许多个处理器与多处理器共享存储器系统的存储器阵列之间的命令和数据的高速传输，其中高速总线系统包括中央单元和连接在多个处理器和共享存储器之间的一系列单向总线，中央单元包括仲裁逻辑和一系列多路复用器，以确定哪些CPU被授权访问共享总线，调度逻辑与仲裁逻辑和多路复用器，以确定哪些CPU被授权访问共享总线，以及端口逻辑，用于组合CPU传输并确定这样的传输是否有效。

8. 发明授权

EP0094177B1 Apparatus for direct memory-to-memory intercomputer communication 失效
标题翻译：用于直接存储器到存储器的互连器通信的装置
公开(公告)号：EP0094177B1
公开(公告)日：1989-07-12
申请号：EP83302411.0
申请日：1983-04-28
申请人： DIGITAL EQUIPMENT CORPORATION
发明人： Strecker, William D. , Stewart, Robert E. , Fuller, Samuel
IPC分类号： G06F15/16
CPC分类号： G06F15/167 , G06F15/177

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