专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

EP0332297B1 Loadable ripple counter 失效
标题翻译：异步计数器预设。
公开(公告)号：EP0332297B1
公开(公告)日：1994-05-18
申请号：EP89301340.9
申请日：1989-02-13
申请人： DIGITAL EQUIPMENT CORPORATION
发明人： Slater, Andrew E.
IPC分类号： H03K23/66 , H03K23/58
CPC分类号： H03K23/58 , H03K23/665

2. 发明公开

EP0332297A3 Loadable ripple counter 失效
标题翻译：负载纹理计数器
公开(公告)号：EP0332297A3
公开(公告)日：1990-12-19
申请号：EP89301340.9
申请日：1989-02-13
申请人： DIGITAL EQUIPMENT CORPORATION
发明人： Slater, Andrew E.
IPC分类号： H03K23/66 , H03K23/58
CPC分类号： H03K23/58 , H03K23/665
摘要： A loadable N-bit ripple counter having N bit subcircuits that each inlude a flip-flop (42, 44, 46) and a bit loading element (48, 50, 52). The flip-flop output is controllable to a known state when a flip-flop control signal is asserted. The bit loading element (48, 50, 52) is connected to receive the flip-flop output (Q) and a bit input of a multibit number (LD0H, LD1H, LD2H) being loaded and to provide a bit output of the counter (CNT0, CNT1, CNT2), the bit output being controlled by the states of the flip-flop output and the bit input, and, except for the most significant bit, serving as a clock for the next more significant bit subcircuit.

3. 发明公开

EP0332297A2 Loadable ripple counter 失效
标题翻译：异步机Zählermit Preset
公开(公告)号：EP0332297A2
公开(公告)日：1989-09-13
申请号：EP89301340.9
申请日：1989-02-13
申请人： DIGITAL EQUIPMENT CORPORATION
发明人： Slater, Andrew E.
IPC分类号： H03K23/66 , H03K23/58
CPC分类号： H03K23/58 , H03K23/665
摘要： A loadable N-bit ripple counter having N bit subcircuits that each inlude a flip-flop (42, 44, 46) and a bit loading element (48, 50, 52). The flip-flop output is controllable to a known state when a flip-flop control signal is asserted. The bit loading element (48, 50, 52) is connected to receive the flip-flop output (Q) and a bit input of a multibit number (LD0H, LD1H, LD2H) being loaded and to provide a bit output of the counter (CNT0, CNT1, CNT2), the bit output being controlled by the states of the flip-flop output and the bit input, and, except for the most significant bit, serving as a clock for the next more significant bit subcircuit.
摘要翻译：一种可负载的N位纹波计数器，具有N位子电路，每个子电路都包含触发器（42,44,46）和位加载元件（48,50,52）。当触发器控制信号被断言时，触发器输出可控制到已知状态。连接比特加载元件（48,50,52）以接收触发器输出（Q）并且加载多位数（LD0H，LD1H，LD2H）的位输入并提供计数器的位输出 CNT0，CNT1，CNT2），位输出由触发器输出和位输入的状态控制，除了最高有效位外，还用作下一个更高有效位子电路的时钟。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式