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1. 发明公开

EP0380858A3 Method and apparatus for detecting and correcting errors in a pipelined computer system 失效
标题翻译：用于检测和校正管道计算机系统中的错误的方法和装置
公开(公告)号：EP0380858A3
公开(公告)日：1991-08-28
申请号：EP89309651.1
申请日：1989-09-22
申请人： DIGITAL EQUIPMENT CORPORATION
发明人： Beaven, Richard C. , Evans, Michael B. , Hetherington, Ricky C. , Fossum, Tryggve
IPC分类号： G06F11/00 , G06F11/14
CPC分类号： G06F11/2236 , G06F9/3863 , G06F11/0724 , G06F11/0772 , G06F11/0781 , G06F11/1405
摘要： In a multiprocessor system, an error occurring in any one of the CPUs may have an impact upon the operation of the remaining CPUs, and therefore these errors must be handled quickly. The errors are grouped into two categories: synchronous errors (those that must be corrected immediately to allow continued processing of the current instruction); and asynchronous errors (those errors that do not affect execution of the current instruction and may be handled upon completing execution of the current instruction). Since synchronous errors prevent continued execution of the current instruction, it is preferable that the last stable state conditions of the faulting CPU be restored and the faulting instruction reexecuted. These stable state conditions advantageously occur between the execution of each instruction. However, in a pipelined computer system, it is difficult to identify the beginning and ending of a selected instruction since multiple instructions are in process at the same time. Accordingly, the execution unit is selected to be the point of synchronization between error handling and instruction execution. Once the error is identified as asynchronous or synchronous and the execution unit allows the instruction to complete or rolls back the state conditions to their preinstruction values, error analyzing software examines the condition of the suspect data latches in the CPU. A serial diagnostic link stops the system clock of the CPU and serially loads the CPU data latches into the System Processor Unit for error determination. Thereafter, the CPU system clock is restarted and the CPU resumes execution.

2. 发明公开

EP0762704A2 A distributed interactive multimedia service system 失效
标题翻译： Verteiltes interaktives Multimediadienstesystem
公开(公告)号：EP0762704A2
公开(公告)日：1997-03-12
申请号：EP96112876.6
申请日：1996-08-09
申请人： DIGITAL EQUIPMENT CORPORATION
发明人： Hooper, Donald F. , Tongel, David M. , Evans, Michael B.
IPC分类号： H04L29/06
CPC分类号： H04L29/06 , H04L67/42
摘要： In a distributed interactive multimedia service system, a client application (11) of a set-top box located at a customer premises generates an attach request (410) . A session manager (205), in response to receiving the attach request via a network, generates an allocation request (440) and a create request (450). A resource manager (210), in response to the allocation request, allocates resources of a plurality of multimedia servers. The resources can include processor, memory, disk, and network resources. A media stream manager (207), in response to the create request, creates a multimedia stream. The session manager, in response to the resources being allocated, and the multimedia stream being created, launches a selected one of a plurality of multimedia services in the plurality of multimedia servers. The selected service provides multimedia information to the set-top box via the multimedia stream. The system includes a memory storing the plurality of multimedia services in a hierarchical tree structure having nodes representing composite and elemental services.
摘要翻译：在分布式交互式多媒体服务系统中，位于客户驻地的机顶盒的客户端应用程序（11）生成附加请求（410）。会话管理器（205）响应于经由网络接收附加请求，生成分配请求（440）和创建请求（450）。资源管理器（210）响应于分配请求分配多个多媒体服务器的资源。资源可以包括处理器，内存，磁盘和网络资源。媒体流管理器（207）响应于创建请求创建多媒体流。会话管理器响应于正在分配的资源和正在创建的多媒体流，在多个多媒体服务器中启动多个多媒体服务中的所选择的一个。所选择的服务通过多媒体流向机顶盒提供多媒体信息。该系统包括以分层树结构存储多个多媒体服务的存储器，其具有表示复合和元素服务的节点。

3. 发明授权

EP0380858B1 Method and apparatus for detecting and correcting errors in a pipelined computer system 失效
标题翻译：根据该控制方法在一个工作的方法和装置用于误差检测和校正重叠的计算机系统。
公开(公告)号：EP0380858B1
公开(公告)日：1994-10-26
申请号：EP89309651.1
申请日：1989-09-22
申请人： DIGITAL EQUIPMENT CORPORATION
发明人： Beaven, Richard C. , Evans, Michael B. , Hetherington, Ricky C. , Fossum, Tryggve
IPC分类号： G06F11/00 , G06F11/14
CPC分类号： G06F11/2236 , G06F9/3863 , G06F11/0724 , G06F11/0772 , G06F11/0781 , G06F11/1405
摘要： In a multiprocessor system, an error occurring in any one of the CPUs may have an impact upon the operation of the remaining CPUs, and therefore these errors must be handled quickly. The errors are grouped into two categories: synchronous errors (those that must be corrected immediately to allow continued processing of the current instruction); and asynchronous errors (those errors that do not affect execution of the current instruction and may be handled upon completing execution of the current instruction). Since synchronous errors prevent continued execution of the current instruction, it is preferable that the last stable state conditions of the faulting CPU be restored and the faulting instruction reexecuted. These stable state conditions advantageously occur between the execution of each instruction. However, in a pipelined computer system, it is difficult to identify the beginning and ending of a selected instruction since multiple instructions are in process at the same time. Accordingly, the execution unit is selected to be the point of synchronization between error handling and instruction execution. Once the error is identified as asynchronous or synchronous and the execution unit allows the instruction to complete or rolls back the state conditions to their preinstruction values, error analyzing software examines the condition of the suspect data latches in the CPU. A serial diagnostic link stops the system clock of the CPU and serially loads the CPU data latches into the System Processor Unit for error determination. Thereafter, the CPU system clock is restarted and the CPU resumes execution.

4. 发明公开

EP0380858A2 Method and apparatus for detecting and correcting errors in a pipelined computer system 失效
标题翻译：根据该控制方法在一个工作的方法和装置用于误差检测和校正重叠的计算机系统。
公开(公告)号：EP0380858A2
公开(公告)日：1990-08-08
申请号：EP89309651.1
申请日：1989-09-22
申请人： DIGITAL EQUIPMENT CORPORATION
发明人： Beaven, Richard C. , Evans, Michael B. , Hetherington, Ricky C. , Fossum, Tryggve
IPC分类号： G06F11/00 , G06F11/14
CPC分类号： G06F11/2236 , G06F9/3863 , G06F11/0724 , G06F11/0772 , G06F11/0781 , G06F11/1405
摘要： In a multiprocessor system, an error occurring in any one of the CPUs may have an impact upon the operation of the remaining CPUs, and therefore these errors must be handled quickly. The errors are grouped into two categories: synchronous errors (those that must be corrected immediately to allow continued processing of the current instruction); and asynchronous errors (those errors that do not affect execution of the current instruction and may be handled upon completing execution of the current instruction). Since synchronous errors prevent continued execution of the current instruction, it is preferable that the last stable state conditions of the faulting CPU be restored and the faulting instruction reexecuted. These stable state conditions advantageously occur between the execution of each instruction. However, in a pipelined computer system, it is difficult to identify the beginning and ending of a selected instruction since multiple instructions are in process at the same time. Accordingly, the execution unit is selected to be the point of synchronization between error handling and instruction execution. Once the error is identified as asynchronous or synchronous and the execution unit allows the instruction to complete or rolls back the state conditions to their preinstruction values, error analyzing software examines the condition of the suspect data latches in the CPU. A serial diagnostic link stops the system clock of the CPU and serially loads the CPU data latches into the System Processor Unit for error determination. Thereafter, the CPU system clock is restarted and the CPU resumes execution.
摘要翻译：在多处理器系统中，一个错误在CPU中的任一项发生的可能对操作来影响其余的CPU，因此本文错误必须快速处理。错误被分为两类：同步的错误（thosethat必须立即纠正，以允许当前指令的继续处理）; 和异步错误（这些错误不影响当前指令的执行做，可能在完成当前指令的执行处理）。由于同步错误防止继续当前指令的执行，优选做的断层CPU的负荷稳定的状态条件被恢复，且该错误指令重新执行。这些稳定状态条件下的每个指令的执行之间有利地好发。然而，在流水线计算机系统中，很难确定一个选择的指令的开始和结束，因为多个指令是在过程中，在Sametime中。因此，执行单元被选择为错误处理和指令执行之间的同步点。一旦错误被识别为同步或异步和所述执行单元允许该指令来完成或回滚该状态条件以它们的preinstruction值，错误分析软件检查CPU中的可疑数据锁存器的状态。串行诊断链路停止CPU的系统时钟和串行加载CPU数据锁存到系统处理器单元对错误确定。那里以后，CPU的系统时钟是重新启动，并且CPU继续执行。

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