发明公开
EP0380858A3 Method and apparatus for detecting and correcting errors in a pipelined computer system
失效 - 权利终止

基本信息:
- 专利标题: Method and apparatus for detecting and correcting errors in a pipelined computer system
- 专利标题(中):用于检测和校正管道计算机系统中的错误的方法和装置
- 申请号:EP89309651.1 申请日:1989-09-22
- 公开(公告)号:EP0380858A3 公开(公告)日:1991-08-28
- 发明人: Beaven, Richard C. , Evans, Michael B. , Hetherington, Ricky C. , Fossum, Tryggve
- 申请人: DIGITAL EQUIPMENT CORPORATION
- 申请人地址: 111 Powdermill Road Maynard Massachusetts 01754-1418 US
- 专利权人: DIGITAL EQUIPMENT CORPORATION
- 当前专利权人: DIGITAL EQUIPMENT CORPORATION
- 当前专利权人地址: 111 Powdermill Road Maynard Massachusetts 01754-1418 US
- 代理机构: Rees, David Christopher
- 优先权: US306828 19890203
- 主分类号: G06F11/00
- IPC分类号: G06F11/00 ; G06F11/14
摘要:
In a multiprocessor system, an error occurring in any one of the CPUs may have an impact upon the operation of the remaining CPUs, and therefore these errors must be handled quickly. The errors are grouped into two categories: synchronous errors (those that must be corrected immediately to allow continued processing of the current instruction); and asynchronous errors (those errors that do not affect execution of the current instruction and may be handled upon completing execution of the current instruction). Since synchronous errors prevent continued execution of the current instruction, it is preferable that the last stable state conditions of the faulting CPU be restored and the faulting instruction reexecuted. These stable state conditions advantageously occur between the execution of each instruction. However, in a pipelined computer system, it is difficult to identify the beginning and ending of a selected instruction since multiple instructions are in process at the same time. Accordingly, the execution unit is selected to be the point of synchronization between error handling and instruction execution. Once the error is identified as asynchronous or synchronous and the execution unit allows the instruction to complete or rolls back the state conditions to their preinstruction values, error analyzing software examines the condition of the suspect data latches in the CPU. A serial diagnostic link stops the system clock of the CPU and serially loads the CPU data latches into the System Processor Unit for error determination. Thereafter, the CPU system clock is restarted and the CPU resumes execution.