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1. 发明公开

EP1831892A4 SYSTEM FOR PERFORMING FAST TESTING DURING FLASH REFERENCE CELL SETTING 审中-公开
标题翻译： SYSTEM FOR执行快速试验FLASH参考单元设置期间
公开(公告)号：EP1831892A4
公开(公告)日：2009-06-10
申请号：EP05848820
申请日：2005-11-18
申请人： ATMEL CORP
发明人： BEDARIDA LORENZO , BARTOLI SIMONE , SURICO STEFANO , FRULIO MASSIMILIANO
IPC分类号： G11C7/14
CPC分类号： G11C7/14 , G11C16/04 , G11C16/28 , G11C29/24 , G11C29/50004 , G11C2029/4002
摘要： An embedded circuit (14) in a memory device (10) is used in place of an external test device to perform time-consuming tasks such as voltage verification during the setting of reference cells (20). An external test device (16) programs at least one reference cell (22) to a predetermined value. The embedded circuit uses the cell (22) programmed by the external device as a comparative reference to program additional reference cells (20).

2. 发明公开

EP1815480A4 METHOD AND SYSTEM FOR REGULATING A PROGRAM VOLTAGE VALUE DURING MULTILEVEL MEMORY DEVICE PROGRAMMING 审中-公开
标题翻译：方法和系统的控制程序的电压值时编程多级内存模块
公开(公告)号：EP1815480A4
公开(公告)日：2009-03-04
申请号：EP05849298
申请日：2005-11-23
申请人： ATMEL CORP
发明人： FRULIO MASSIMILIANO , BARTOLI SIMONE , MANFR DAVID , SACCO ANDREA
IPC分类号： G11C11/56 , G11C5/14 , G11C16/12
CPC分类号： G11C16/12 , G11C5/145 , G11C11/5628 , G11C16/04 , G11C16/30 , G11C16/3459 , G11C29/02 , G11C29/021 , G11C29/028
摘要： Regulating a program voltage value during multilevel memory device programming includes utilizing a program path duplicate in an output pump regulator circuit. Further, the output pump regulator circuit is utilized to provide a regulated program voltage for memory cell programming, the regulated program voltage correcting for a program path voltage drop and compensating for temperature variation.

3. 发明公开

EP1537671A4 DAC-BASED VOLTAGE REGULATOR FOR FLASH MEMORY ARRAY 有权
标题翻译： ON DAC基于电压稳压器由于F R快闪存储器阵列
公开(公告)号：EP1537671A4
公开(公告)日：2006-01-11
申请号：EP03749600
申请日：2003-09-09
申请人： ATMEL CORP
发明人： FRULIO MASSIMILIANO , SIVERO STEFANO , BARTOLI SIMONE , MOGNONI SABINA
IPC分类号： G11C16/06 , G05F20060101 , G11C5/14 , G11C16/30 , G11C16/34 , H02M3/07 , H03M1/66
CPC分类号： G11C16/30 , G11C5/147 , H02M3/07
摘要： A DAC-based voltage regulator system for a non-volatile memory device comprises a charge pump circuit having an enable input and a voltage output node. A voltage-to current converter has an input coupled to the voltage output node and an output coupled to a virtual ground node. A current source is coupled to the virtual ground node and sinks one of a plurality of currents in response to states of a plurality of digital input signals. A transconductance amplifier has an inverting input at the virtual ground node, a non-inverting input coupled to a reference voltage potential, and an output. A comparator has a first input coupled to the output of the transconductance amplifier, a second input coupled to a reference voltage potential, and an output coupled to the enable input of said charge pump.

4. 发明公开

EP1550017A4 NEGATIVE CHARGE PUMP WITH BULK BIASING 审中-公开
标题翻译： NEGATIV-LADUNGSPUMPE MITHAUPTKÖRPERVORSPANNUNG
公开(公告)号：EP1550017A4
公开(公告)日：2007-06-27
申请号：EP03759460
申请日：2003-09-18
申请人： ATMEL CORP
发明人： ODDONE GIORGIO , FRULIO MASSIMILIANO , FIGINI LUCA , TASSAN CASER FABIO
IPC分类号： H02M3/07 , G05F1/10 , H02M3/18
CPC分类号： H02M3/073 , H02M2003/071 , H02M2003/075 , H02M2003/078
摘要： An n-channel MOS transistor negative-voltage charge pump is disclosed in which the bulks of the n-channel MOS transistors (26, 28) are biased in such a manner as to prevent turning on the parasitic bipolar transistor inherent in the CMOS environment of the charge pump structure.
摘要翻译：公开了一种n沟道MOS晶体管负电压电荷泵，其中n沟道MOS晶体管（26,28）的块体以这种方式偏置，以防止导通CMOS环境中固有的寄生双极晶体管电荷泵结构。

5. 发明公开

EP1636903A4 REGENERATIVE CLOCK REPEATER 有权
标题翻译： REGENERATIVERTAKTZWISCHENVERSTÄRKER
公开(公告)号：EP1636903A4
公开(公告)日：2007-03-28
申请号：EP04752608
申请日：2004-05-18
申请人： ATMEL CORP
发明人： SIVERO STEFANO , FRULIO MASSIMILIANO
IPC分类号： H03K5/01 , G06F1/10 , H01L20060101 , H03K17/16 , H03K19/017
CPC分类号： H03K19/01721 , G06F1/10
摘要： A regenerative clock repeater (Fig. 5; 700) comprises an edge detector (Fig. 6; 500) and an output driver means (706) to produce the clock signal (CK) by recovering its high logical level and low logical level. The output driver means further comprises a pull-up (706A) and a pull-down (706B) circuitry adapted to receive a pair of control signals (PULL-UP#, PULL-DOWN#). These control signals are generated by the edge detector to sense the rising edge and falling edge of the clock signal. Inside the edge detector, a pair of threshold level detectors (540, 550) detect a high and a low logical level of the clock signal and inputs the results to a combination of logic gates (562, 564, 568, 570) and a latch (566) to keep the locations of the signal markers fixed. These fixed-location of control signals trigger the output driver means to recover the high logical level and the low logical level of said clock signal.
摘要翻译：再生时钟中继器（图5; 700）包括边缘检测器（图6; 500）和输出驱动器装置（706），以通过恢复其高逻辑电平和低逻辑电平来产生时钟信号（CK）。输出驱动器装置还包括适用于接收一对控制信号（上拉＃，下拉＃）的上拉（706A）和下拉（706B）电路。这些控制信号由边缘检测器产生以感测时钟信号的上升沿和下降沿。在边缘检测器内部，一对阈值电平检测器（540,550）检测时钟信号的高和低逻辑电平，并将结果输入到逻辑门（562,564,568,570）和锁存器（566）保持信号标记的位置固定。控制信号的这些固定位置触发输出驱动器装置以恢复所述时钟信号的高逻辑电平和低逻辑电平。

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