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1. 发明公开

EP0720051A3 Self-aligned opaque regions for attenuating phase-shifting masks 失效
标题翻译：对于衰减相移掩膜调心渗透区域
公开(公告)号：EP0720051A3
公开(公告)日：1997-04-16
申请号：EP95309007.3
申请日：1995-12-12
申请人： AT&T Corp.
发明人： DeMarco, John J. , Kostelak, Robert L. Jr. , Kook, Taeho
IPC分类号： G03F1/00
CPC分类号： G03F1/32
摘要： An attenuating phase-shifting optical lithographic mask is fabricated, in a specific embodiment of the invention, by first depositing a uniformly thick molybdenum silicide layer (11) on a top planar surface of quartz (10). The molybdenum silicide layer has a thickness sufficient for acting as an attenuating (partially transparent) layer in a phase-shifting mask. A uniformly thick chromium layer (12) is deposited on the molybdenum silicide layer. The chromium layer has a thickness sufficient for acting as an opaque layer in the phase-shifting mask. Next, the chromium layer is patterned by dry or wet etching, while the chromium is selectively masked with a first patterned resist layer (13). Then the molybdenum silicide layer is patterned by dry or wet etching, using the resulting patterned chromium layer as a protective layer, whereby a composite layer of molybdenum silicide and chromium is formed having mutually separated composite stripes (31, 32). Any remaining resist is removed. Next the top and sidewall surfaces of some, but not others, of these mutually separated stripes are coated with a second patterned resist layer (15). Finally (FIG. 6), the chromium layer, but not the molybdenum silicide layer, is removed from the others of the mutually separated composite stripes.

2. 发明公开

EP0420489A3 Compensation of lithographic and etch proximity effects 有权转让
标题翻译：光刻和蚀刻接近效应的补偿
公开(公告)号：EP0420489A3
公开(公告)日：1992-04-15
申请号：EP90310242.4
申请日：1990-09-19
申请人： AT&T Corp.
发明人： Eisenberg, Juli Hong , Fritzinger, Larry Bruce , Fu, Chong-Cheng , Kook, Taeho , Wolf, Thomas Michael
IPC分类号： G03F7/20
CPC分类号： G03F7/20 , Y10S438/941 , Y10S438/948
摘要： In the manufacture of integrated-circuit devices, patterned features are made on a substrate by etching a deposited layer. The pattern comprises features which are closely spaced, as well as others which are more isolated. Etching is in approximate conformance with a lithographically defined resist pattern which in turn is in approximate conformance with a desired pattern. A processing parameter such as, e.g., resist layer thickness is chosen such that an etched pattern is obtained which approximates a desired pattern more closely than a lithographically defined resist pattern.

3. 发明公开

EP0766138A2 Spun-on glass layer as a dry etch-mask, for fabricating a metallic mask by means of a bi-level process 失效
标题翻译：旋转玻璃Schicht alsTrockenätzmaskezur Herstellung einer metallischen Maske mittels eines Zweilagenverfahrens
公开(公告)号：EP0766138A2
公开(公告)日：1997-04-02
申请号：EP96306755.8
申请日：1996-09-17
申请人： AT&T Corp.
发明人： Kook, Taeho
IPC分类号： G03F1/08 , G03F7/09
CPC分类号： G03F1/80 , G03F7/094
摘要： A metallic mask is fabricated by using a patterned spun-on glass layer located on an initially uniformly thick metallic layer. In turn, the metallic layer is located on a transparent substrate such as quartz. Patterning of the spun-on glass layer is performed by means of an anistropic dry-etching step, using (as a dry-etch protective layer) an overlying patterned resist that has been patterned by means of a direct-writing electron beam followed by wet development. The patterned spun-on glass layer is used as a dry-etch protective layer during a subsequent anisotropic dry-etch patterning of the metallic layer. After the metallic layer thus has been patterned, the spun-on glass layer can be removed by means of a dilute aqueous solution of hydrofluoric acid.
摘要翻译：通过使用位于最初均匀厚度的金属层上的图案旋涂玻璃层来制造金属掩模。反过来，金属层位于诸如石英的透明基板上。旋涂玻璃层的图案通过使用（作为干蚀刻保护层）的已经通过直写式电子束图案化的上覆图案化抗蚀剂的干性蚀刻步骤进行，然后湿润发展。在金属层的随后的各向异性干蚀刻图案化期间，将图案化的旋涂玻璃层用作干蚀刻保护层。在金属层被图案化之后，可以通过稀氢氟酸水溶液去除纺丝玻璃层。

4. 发明公开

EP0720051A2 Self-aligned opaque regions for attenuating phase-shifting masks 失效
标题翻译： SelbstausrichtendeundurchlässigeBereichefürgedämpftePhasenverschiebungsmasken
公开(公告)号：EP0720051A2
公开(公告)日：1996-07-03
申请号：EP95309007.3
申请日：1995-12-12
申请人： AT&T Corp.
发明人： DeMarco, John J. , Kostelak, Robert L. Jr. , Kook, Taeho
IPC分类号： G03F1/00
CPC分类号： G03F1/32
摘要： An attenuating phase-shifting optical lithographic mask is fabricated, in a specific embodiment of the invention, by first depositing a uniformly thick molybdenum silicide layer (11) on a top planar surface of quartz (10). The molybdenum silicide layer has a thickness sufficient for acting as an attenuating (partially transparent) layer in a phase-shifting mask. A uniformly thick chromium layer (12) is deposited on the molybdenum silicide layer. The chromium layer has a thickness sufficient for acting as an opaque layer in the phase-shifting mask. Next, the chromium layer is patterned by dry or wet etching, while the chromium is selectively masked with a first patterned resist layer (13). Then the molybdenum silicide layer is patterned by dry or wet etching, using the resulting patterned chromium layer as a protective layer, whereby a composite layer of molybdenum silicide and chromium is formed having mutually separated composite stripes (31, 32). Any remaining resist is removed. Next the top and sidewall surfaces of some, but not others, of these mutually separated stripes are coated with a second patterned resist layer (15). Finally (FIG. 6), the chromium layer, but not the molybdenum silicide layer, is removed from the others of the mutually separated composite stripes.
摘要翻译：在本发明的具体实施例中，通过首先在石英（10）的顶部平坦表面上沉积均匀厚的硅化钼层（11）来制造衰减相移光学光刻掩模。硅化钼层具有足以用作相移掩模中的衰减（部分透明）层的厚度。均匀厚的铬层（12）沉积在硅化钼层上。铬层具有足以在相移掩模中用作不透明层的厚度。接下来，通过干蚀刻或湿蚀刻对铬层进行图案化，同时用第一图案化抗蚀剂层（13）选择性地掩蔽铬。然后通过干蚀刻或湿蚀刻将钼硅化物层图案化，使用所得图案化的铬层作为保护层，由此形成具有相互分离的复合条纹（31,32）的硅化钼和铬的复合层。任何剩余的抗蚀剂被去除。接下来，这些相互分离的条纹的一些而不是其他的顶表面和侧壁表面涂覆有第二图案化抗蚀剂层（15）。最后（图6），从相互分离的复合条纹中的其它部分去除铬层而不是硅化钼层。

5. 发明公开

EP0605123A3 Method for integrated circuit fabrication including linewidth control during etching 失效
标题翻译：用于集成电路制造的方法，包括在蚀刻期间的线性控制。
公开(公告)号：EP0605123A3
公开(公告)日：1995-10-25
申请号：EP93309855.0
申请日：1993-12-08
申请人： AT&T Corp.
发明人： Kook, Taeho , Kornbilt, Avinoam , Olasupo, Kolawole Rahman
IPC分类号： G03F7/09 , G03F7/36
CPC分类号： H01L21/31138 , H01L21/32139
摘要： Pattern transfer from a resist to an underlying layer is accomplished by etching the resist in a plasma comprising hydrogen bromide and oxygen.

6. 发明公开

EP0605123A2 Method for integrated circuit fabrication including linewidth control during etching 失效
标题翻译：一种用于制造集成电路与该行的控制过程中，图案形成步骤宽度测量。
公开(公告)号：EP0605123A2
公开(公告)日：1994-07-06
申请号：EP93309855.0
申请日：1993-12-08
申请人： AT&T Corp.
发明人： Kook, Taeho , Kornbilt, Avinoam , Olasupo, Kolawole Rahman
IPC分类号： G03F7/09 , G03F7/36
CPC分类号： H01L21/31138 , H01L21/32139
摘要： Pattern transfer from a resist to an underlying layer is accomplished by etching the resist in a plasma comprising hydrogen bromide and oxygen.
摘要翻译：从在下面的层的抗蚀剂图案转印是通过蚀刻在等离子体包含溴化氢和氧的抗蚀剂来完成的。

7. 发明授权

EP0506287B1 Method of fabricating semiconductor devices and integrated circuits using sidewall spacer technology 有权转让
标题翻译：一种用于生产半导体器件和使用侧壁间隔件的集成电路的过程
公开(公告)号：EP0506287B1
公开(公告)日：1997-03-05
申请号：EP92302308.9
申请日：1992-03-18
申请人： AT&T Corp.
发明人： Chen, Min-Liang , Chittipeddi, Sailesh , Kook, Taeho , Powell, Richard Allyn , Kumar Roy, Pradip
IPC分类号： H01L21/28 , H01L21/336 , H01L29/78 , H01L29/43
CPC分类号： H01L29/66825 , H01L21/28176 , H01L21/28273 , H01L27/115 , H01L29/6656 , H01L29/6659

8. 发明公开

EP0506287A1 Method of fabricating semiconductor devices and integrated circuits using sidewall spacer technology 有权转让
标题翻译： Halbleiteranordnungen und integrierte Schaltkreise mit Verwendung von Seitenwand-Abstandsstücken。
公开(公告)号：EP0506287A1
公开(公告)日：1992-09-30
申请号：EP92302308.9
申请日：1992-03-18
申请人： AT&T Corp.
发明人： Chen, Min-Liang , Chittipeddi, Sailesh , Kook, Taeho , Powell, Richard Allyn , Kumar Roy, Pradip
IPC分类号： H01L21/28 , H01L21/336 , H01L29/78 , H01L29/62
CPC分类号： H01L29/66825 , H01L21/28176 , H01L21/28273 , H01L27/115 , H01L29/6656 , H01L29/6659
摘要： The base layer of high quality spacers, such as those used on the sidewalls of the gate stack of submicron devices (e.g. MOSFETs, EPROMs), are formed as composite, multi-layered structures (22.1-22.3) of silicon oxides or of silicon oxides and silicon nitride.
摘要翻译：诸如在亚微米器件（例如，MOSFET，EPROM）的栅极堆叠的侧壁上使用的高质量间隔物的基底层形成为氧化硅或氧化硅的复合多层结构（22.1-22.3）和氮化硅。

9. 发明公开

EP0420489A2 Compensation of lithographic and etch proximity effects 有权转让
标题翻译： Kompensation von lithographischen undÄtznäheeffekten。
公开(公告)号：EP0420489A2
公开(公告)日：1991-04-03
申请号：EP90310242.4
申请日：1990-09-19
申请人： AT&T Corp.
发明人： Eisenberg, Juli Hong , Fritzinger, Larry Bruce , Fu, Chong-Cheng , Kook, Taeho , Wolf, Thomas Michael
IPC分类号： G03F7/20
CPC分类号： G03F7/20 , Y10S438/941 , Y10S438/948
摘要： In the manufacture of integrated-circuit devices, patterned features are made on a substrate by etching a deposited layer. The pattern comprises features which are closely spaced, as well as others which are more isolated. Etching is in approximate conformance with a lithographically defined resist pattern which in turn is in approximate conformance with a desired pattern. A processing parameter such as, e.g., resist layer thickness is chosen such that an etched pattern is obtained which approximates a desired pattern more closely than a lithographically defined resist pattern.
摘要翻译：在集成电路器件的制造中，通过蚀刻沉积层在衬底上形成图案化特征。该图案包括紧密间隔的特征，以及更孤立的其他特征。蚀刻大致符合光刻定义的抗蚀剂图案，其又与所需图案大致一致。选择诸如抗蚀剂层厚度的处理参数，使得获得蚀刻图案，其近似于光刻定义的抗蚀剂图案的期望图案。

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