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81. 发明授权

EP1365512B1 Schaltungsanordnung zum Abschluss von Busleitungen eines Bussystems 有权
标题翻译：在电路的总线系统的总线的端
公开(公告)号：EP1365512B1
公开(公告)日：2008-03-19
申请号：EP03011656.0
申请日：2003-05-22
申请人： SIEMENS AKTIENGESELLSCHAFT
发明人： Reichl, Wolfgang
IPC分类号： H03K19/0175
CPC分类号： G06F13/4086 , H04L25/0298

82. 发明公开

EP1635466A3 Digitale Programmierschnittstelle zwischen einem Basisbandprozessor und einem integrierten Hochfrequenzbaustein 有权转让
标题翻译：基带处理器和一个集成的射频模块之间数字编程接口
公开(公告)号：EP1635466A3
公开(公告)日：2007-08-08
申请号：EP05016339.3
申请日：2005-07-27
申请人： Infineon Technologies AG
发明人： Grossmann, Timo , Stögmüller, Johannes
IPC分类号： H03K19/0175 , G06F3/00
CPC分类号： G06F13/4291
摘要： Ein Schaltkreis nimmt ein Taktsignal, ein Datenwort, welches von einer Steuereinrichtung ausgegeben wird und welches Informationen über einen Lese- oder Schreibzugriff auf den Schaltkreis umfasst, und ein Freigabesignal, welches während der Übertragung des Datenworts einen vorgegebenen Wert aufweist, entgegen. Eine Bestimmungseinheit (CLK_CNT, RW_DECODE) bestimmt anhand der Anzahl der Takte des Taktsignals, während welcher das Freigabesignal den vorgegebenen Wert aufweist, welcher digitale Schnittstellen-Standard dem während dieser Takte übertragenen Datenwort zugrunde liegt.

83. 发明公开

EP1782535A2 HIGH SPEED INTEGRATED CIRCUIT 审中-公开
标题翻译： RAPID集成电路
公开(公告)号：EP1782535A2
公开(公告)日：2007-05-09
申请号：EP05773377.6
申请日：2005-06-16
申请人： Kao, Richard
发明人： Kao, Richard
IPC分类号： H03K17/16 , H03K19/0175
CPC分类号： H03K19/0948 , H03K19/018578
摘要： A novel driver circuit that uses a differential driver as a design backbone is described. Unlike a conventional differential interface, which typically has two or more outputs for providing an output signal and its complement, one of the differential driver's outputs is coupled to drive an output signal onto a signal line (22a), while another one of the differential driver's outputs is unused and terminated (22b), for instance by coupling the output to package ground or a voltage source via a capacitor. The performance of the driver circuit is significantly improved over conventional singled-ended driver designs.

84. 发明公开

EP1751864A2 APPARATUS AND METHOD FOR SHIFTING A SIGNAL FROM A FIRST REFERENCE LEVEL TO A SECOND REFERENCE LEVEL 有权
标题翻译：设备技术的信号转换从第一参考电平第二参考电平
公开(公告)号：EP1751864A2
公开(公告)日：2007-02-14
申请号：EP05745423.3
申请日：2005-05-02
申请人： TEXAS INSTRUMENTS INCORPORATED
发明人： FATTARUSO, John, W. , SHEAHAN, Benjamin, J.
IPC分类号： H03K19/0175
CPC分类号： H03K19/0136 , H03K17/04126 , H03K19/00346 , H03K19/00376 , H03K19/01812 , Y10T307/826
摘要： A level-shifting apparatus 80 includes an input section 82, level shift sections 84 and output sections 86. Differential signaling input signals received from an upstream data source at input terminals 100, 102 of input section 82 are coupled with respective bases of common emitter NPN bipolar transistors Q1, Q2 and respectively presented at collector outputs 124, 126 to level shift sections 84. Each level shift section 84 includes a low speed network 130 and a high speed network 140 coupled substantially in parallel between a respective output 124, 126 and an output locus 88. Low speed network 130 operates as a level setting signal path to set the DC (direct current) level at output locus 88 to a desired level. Low speed network 130 employs an active amplifier component to set output DC resistance. In one embodiment, the active component is an NPN bipolar transistor Q4 configured as an emitter-follower, with its base connected to an output 124, 126 via a resistor RLS. High speed network 140 operates as a signal transition path to speed up provision of signal transitions (for example, information bearing signal transitions) to output locus 88. In one embodiment, a base 142 of an NPN bipolar transistor Q5 is driven without added series resistance to avoid delay and unwanted filtering. Output section 86 connects signals appearing at output locus 88 with downstream portions of a communication system.

85. 发明公开

EP1628399A4 SEMICONDUCTOR DEVICE 有权
标题翻译： HALBLEITERBAUELEMENT
公开(公告)号：EP1628399A4
公开(公告)日：2006-07-26
申请号：EP03730682
申请日：2003-05-28
申请人： FUJITSU LTD
发明人： UNO OSAMU
IPC分类号： H03K19/00 , H01L27/04 , H03K19/003 , H03K19/0175
CPC分类号： H03K19/00315 , H03K17/0822 , H03K17/102
摘要： A semiconductor device having a terminal BUS being inputted with an applying voltage VBUS higher than a power supply voltage VDD, wherein a gate terminal G4 is applied with the power supply voltage VDD minus a threshold voltage Vthn when the voltage VBUS is lower than the power supply voltage VDD plus a threshold voltage Vthp and a PMOS transistor P4 is conducted. A gate terminal G2 is supplied with the power supply voltage VDD and a PMOS transistor P2 is turned off. When the voltage VBUS is equal to or higher than the power supply voltage VDD plus the threshold voltage Vthp, the PMOS transistor P4 is turned off by supplying the voltage VBUS to the gate terminal G4, while furthermore, a PMOS transistor P3 is conducted and the PMOS transistor P4 is turned off by supplying the voltage VBUS to the gate terminal G2. Unnecessary leak current is not fed from the terminal BUS regardless of the applying voltage VBUS and a correct voltage level can be sustained.
摘要翻译：一种具有端子BUS的半导体器件被输入高于电源电压VDD的施加电压VBUS，其中当电压VBUS低于电源时，栅极端子G4被施加电源电压VDD减去阈值电压Vthn 电压VDD加上阈值电压Vthp和PMOS晶体管P4。向栅极端子G2提供电源电压VDD，并且PMOS晶体管P2截止。当电压VBUS等于或高于电源电压VDD加上阈值电压Vthp时，通过将电压VBUS提供给栅极端子G4，PMOS晶体管P4截止，而此外，PMOS晶体管P3导通，并且通过将电压VBUS提供给栅极端子G2来关闭PMOS晶体管P4。不管施加电压VBUS如何，都不会从端子BUS馈送不必要的泄漏电流，并且可以维持正确的电压电平。

86. 发明公开

EP1386402A4 MODIFIED REPETITIVE CELL MATCHING TECHNIQUE FOR INTEGRATED CIRCUITS 有权
标题翻译：改进的，重复的细胞比较时技术集成电路
公开(公告)号：EP1386402A4
公开(公告)日：2006-06-07
申请号：EP02769266
申请日：2002-04-12
申请人： ANALOG DEVICES INC
发明人： KRANZ RODNEY LOUIS , LANE CHARLES D , JARMAN DAVID
IPC分类号： H03K19/0175 , H03M1/36 , H03M1/06
CPC分类号： H03M1/0678 , H03M1/36
摘要： An integrated circuit including a number of repetitive cells for producing output signals in response to respective inputs, each cell(14,16,18) having associated with it an output circuit responsive to the cell output signal to produce an output circuit output signal, each of the output circuits including a circuit device having two terminals to provide for the flow therethrough of a current from an associated current supply(137) and producing a corresponding output signal; the improvement for producing the effectsof cell mismatch and output circuit mismatch including an impedance network(150), having a set of impedance elements each connected between corresponding terminals or respective pairs of the circuits with each circuit device forming a part of a respective output circuit(110,112), the impedance elements reducing the efforts of cell mismatch and output circuit mismatch on the output signals; there maybe one impedance network which accommodates mismatch es in both the cell and output circuits or there may be one impedance network to accommodate cell mismatch and another to accommodate output circuit mismatch.

87. 发明公开

EP1470643A4 METHOD AND APPARATUS FOR COMMUNICATION USING A DISTRIBUTED MULTIPLEXED BUS 审中-公开
标题翻译：方法和装置通讯都通过分布式总线复用
公开(公告)号：EP1470643A4
公开(公告)日：2006-05-31
申请号：EP03703933
申请日：2003-01-21
申请人： SONICS INC
发明人： EBERT JEFFREY A , ROSSEEL GEERT , MEYER MICHAEL J
IPC分类号： G06F3/00 , G06F13/40 , H03K19/0175
CPC分类号： G06F13/4045
摘要： An apparatus having a first and second bus is disclosed. In one embodiment, multiple units are coupled to the first and second buses. The units include a middle unit and two side units. Each side unit has a first bus output coupled to a first bus input of the middle unit. The middle unit has a second bus output coupled to a second bus input of each side unit.

88. 发明授权

EP0789951B1 PCMCIA AUTOCONFIGURE PC CARD 失效
标题翻译： PC-卡，PCMCIA自行设定
公开(公告)号：EP0789951B1
公开(公告)日：2006-03-29
申请号：EP95939138.4
申请日：1995-11-03
申请人： INTEL CORPORATION
发明人： GAFKEN, Andrew, H. , MCGRATH, John, H.
IPC分类号： H03K19/0175 , G06F13/40
CPC分类号： G06F13/385
摘要： A System for enabling a PC card (10) to approximately function in the 16-bit and 32-bit standard PCMCIA environments. If the 16-bit standard and the 32-bit standard requires a pin to be connected in a certain manner, then the pin is connected in that manner. If the 16-bit standard requires a card detect pin (24) to be grounded and the 32-bit standard requires that same card detect pin (24) to be connected to a voltage sense pin (26), then the card detect pin and voltage sense pin are connected (26), and the card detect pin (24) is connected to ground via a pull-down resistor. After initialization, the standard of the PCMCIA adapter (12) can be detected by sensing the voltage of an open-circuited voltage sense pin.

89. 发明公开

EP1635466A2 Digitale Programmierschnittstelle zwischen einem Basisbandprozessor und einem integrierten Hochfrequenzbaustein 有权转让
公开(公告)号：EP1635466A2
公开(公告)日：2006-03-15
申请号：EP05016339.3
申请日：2005-07-27
申请人： Infineon Technologies AG
发明人： Grossmann, Timo , Stögmüller, Johannes
IPC分类号： H03K19/0175 , G06F3/00
CPC分类号： G06F13/4291
摘要： Ein Schaltkreis nimmt ein Taktsignal, ein Datenwort, welches von einer Steuereinrichtung ausgegeben wird und welches Informationen über einen Lese- oder Schreibzugriff auf den Schaltkreis umfasst, und ein Freigabesignal, welches während der Übertragung des Datenworts einen vorgegebenen Wert aufweist, entgegen. Eine Bestimmungseinheit (CLK_CNT, RW_DECODE) bestimmt anhand der Anzahl der Takte des Taktsignals, während welcher das Freigabesignal den vorgegebenen Wert aufweist, welcher digitale Schnittstellen-Standard dem während dieser Takte übertragenen Datenwort zugrunde liegt.
摘要翻译：电路具有用于时钟信号的第一输入（CLK），用于由控制装置产生的数据字的第二输入（DATA），并且提供关于对电路的读写访问的信息和第三输入（STROBE）用于在传送数据字期间输入释放信号。确定单元被设计为在接收到释放信号时确定要使用哪个数字接口标准，并且使用该接口来接收数据字。还包括以下独立权利要求： - （A）使用控制装置产生读取和写入访问以产生数据字的系统; （B）确定在信号编码期间使用的数字间隔标准的方法。

90. 发明公开

EP1564884A4 DIFFERENTIAL CIRCUIT AND RECEIVER WITH SAME 审中-公开
标题翻译： DIFFERENTIALSCHALTUNG UNDEMPFÄNGERDAMIT
公开(公告)号：EP1564884A4
公开(公告)日：2006-01-18
申请号：EP03770036
申请日：2003-10-30
申请人： THINE ELECTRONICS INC
发明人： OKAMURA JUN-ICHI
IPC分类号： H03K19/0175 , H03F3/30 , H03F3/45 , H03F3/68 , H03K19/0948
CPC分类号： H03F3/3028 , H03F3/3064 , H03F3/4521
摘要： Additionally provided are first and second current-supply circuits (51, 52) for introducing constant currents through load resistors (103, 113, 104, 114) if the common-mode voltage at the input stage exceeds the operating ranges of N-channel/P-channel differential amplifier circuits (1, 2). Such a circuit structure can be an equivalent circuit equivalent to structures where a constant current biased P-channel MOS transistor is connected as a load element to an N-channel of a complementary source-follower circuit (15) at the output stage.
摘要翻译：当输入电路的共模电压超过N的工作范围的1/2时，添加第一和第二电流供应电路51和52以向负载电阻103,104,113和104引入恒定电流通道/ P沟道差分放大器电路。因此，即使在上述情况下，也可以通过将输出电路的互补源极跟随器电路15中的N沟道MOS晶体管连接到恒定电流偏置P沟道MOS晶体管的结构来实现等效电路作为负载元件。

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