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81. 发明公开

EP2128986A1 INPUT/OUTPUT CIRCUIT DEVICE 审中-公开
标题翻译： EINGABE- / AUSGABESCHALTUNGSEINRICHTUNG
公开(公告)号：EP2128986A1
公开(公告)日：2009-12-02
申请号：EP07714805.4
申请日：2007-02-22
申请人： Fujitsu Limited
发明人： KIBUNE, Masaya
IPC分类号： H03K19/0175
CPC分类号： H03K19/018528 , H03K19/0175
摘要： The object is to provide an input and output circuit apparatus that can optimally adjust a signal supplied to the input and output circuit without being affected manufacturing variation. An input and output circuit apparatus includes a signal generating circuit configured to generate a first signal, an input and output circuit configured to receive the first signal from the signal generating circuit and a second signal to generate an output signal responsive to the first signal and the second signal, an operation test circuit having substantially an identical circuit configuration to the input and output circuit, and configured to receive the first signal from the signal generating circuit and a third signal to generate an output signal responsive to the first signal and the third signal, a check circuit configured to generates a check signal indicative of an operating condition of the operation test circuit in response to the output signal of the operation test circuit, and an adjustment circuit configured to adjust the signal generating circuit in response to the check signal output from the check circuit.
摘要翻译：本发明的目的是提供一种输入和输出电路设备，其可以最佳地调整提供给输入和输出电路的信号，而不会影响制造变化。输入和输出电路设备包括：信号发生电路，被配置为产生第一信号;输入和输出电路，被配置为从信号发生电路接收第一信号;以及第二信号，以响应于第一信号和第二信号，操作测试电路，其具有与输入和输出电路基本相同的电路配置，并且被配置为从信号发生电路接收第一信号和第三信号，以响应于第一信号和第三信号产生输出信号，检测电路，被配置为响应于所述操作测试电路的输出信号产生指示所述操作测试电路的操作条件的检查信号;以及调整电路，被配置为响应于所述检查信号输出来调整所述信号发生电路从检查电路。

82. 发明授权

EP1308847B1 Computer bus configuration and input/output buffer 失效
标题翻译： Rechnerbuskonfiguration和输入/输出驱动器
公开(公告)号：EP1308847B1
公开(公告)日：2009-11-04
申请号：EP03000313.1
申请日：1996-11-20
申请人： Fujitsu Microelectronics Limited
发明人： Taguchi, Masao, c/o Fujitsu Limited
IPC分类号： G06F13/40 , H03K19/0175
CPC分类号： G11C7/1057 , G06F13/4077 , G06F13/4086 , G11C7/1051 , G11C2207/2227 , H03K19/0016 , H03K19/017545 , H03K19/018585 , Y02D10/14 , Y02D10/151
摘要： An input buffer circuit is disclosed which is connected to a bus for receiving signals from the bus. The input buffer circuit comprises a first buffer (40, 43) for receiving the signals, the first buffer (40, 43) being operable in a first mode in which the signals are transmitted on the bus (10) at a first frequency, a second buffer (41, 44) for receiving the signals, the second buffer (41, 44) being operable in a second mode in which said signals are transmitted on said bus (10) at a second frequency lower than the first frequency, and means (24) for providing one of an output of the first buffer (40, 43) and an output of the second buffer (41, 44) to an internal circuit. The power consumption of the second buffer (41, 44) during operation thereof is lower than power consumption of the first buffer (40, 43) during operation thereof. A corresponding output buffer circuit is also disclosed.

83. 发明公开

EP1743422A4 LOW LEAKAGE AND DATA RETENTION CIRCUITRY 有权转让
标题翻译：泄漏ARMS和数据保持电路
公开(公告)号：EP1743422A4
公开(公告)日：2009-05-20
申请号：EP05711776
申请日：2005-01-20
申请人： MOSAID TECHNOLOGIES CORP
发明人： HOBERMAN BARRY , HILLMAN DANIEL , WALKER WILLIAM , CALLAHAN JOHN , ZAMPAGLIONE MICHAEL , COLE ANDREW
IPC分类号： H03K19/0175 , H03K3/356 , H03K17/10 , H03K19/20
CPC分类号： H03K19/0016
摘要： An integrated circuit includes first circuitry and sleep transistor circuitry. The first circuitry receives input signals and processes the input signals. The first circuitry also retains data in a sleep state that has low leakage. The sleep transistor circuitry is coupled to the first circuitry and receives a sleep signal that has a negative voltage. The sleep circuitry reduces power consumption of the first circuitry in the sleep state to have low leakage based on the sleep signal while retaining the data in the first circuitry.

84. 发明授权

EP1048109B1 CURRENT CONTROL TECHNIQUE 有权
标题翻译：电源控制技术
公开(公告)号：EP1048109B1
公开(公告)日：2009-04-22
申请号：EP98942306.6
申请日：1998-08-27
申请人： RAMBUS INC.
发明人： GARRETT, Billy, Wayne, Jr. , DILLON, John, B. , CHING, Michael, Tak-Kei , STONECYPHER, William, F. , CHAN, Andy, Peng-Pui , GRIFFIN, Matthew, M.
IPC分类号： H03K19/0175 , H03K19/0185 , H03K19/003
CPC分类号： H04L25/028 , G06F13/4077 , G11C7/1051 , G11C7/1057 , G11C7/106 , H03K19/00384 , H04L25/0266
摘要： An output driver circuit and current control technique to facilitate high-speed buses with low noise is used to interface with high-speed dynamic RAMs (DRAMs). The architecture includes the following components: an input isolation block (120), an analog voltage divider (104), an input comparator (125), a sampling latch (130), a current control counter (115), and a bitwise output driver (output driver A 107 and output driver B 111).

85. 发明公开

EP2030323A2 DYNAMIC PERIPHERAL FUNCTION REMAPPING TO EXTERNAL INPUT-OUTPUT CONNECTIONS OF AN INTEGRATED CIRCUIT DEVICE 有权
标题翻译：集成电路的动态PERIPHERIEFUNKTIONSUMABBILDUNG外部输入输出连接
公开(公告)号：EP2030323A2
公开(公告)日：2009-03-04
申请号：EP07762367.6
申请日：2007-05-31
申请人： Microchip Technology Incorporated
发明人： WOJEWODA, Igor , BOLES, Brian , BRADLEY, Steve , KAVAIYA, Gaurang
IPC分类号： H03K19/0175
CPC分类号： H03K19/17764 , H03K19/1732 , H03K19/17744
摘要： Peripheral functions of an integrated circuit device may be pooled and dynamically mapped to available external input-output connections of the integrated circuit device by using a set of configuration registers. To provide system robustness, the configuration registers may implement various levels of write protection, error correction and monitoring circuitry. One or more peripheral output functions may be mapped to one or more external output connections. Not more than one output function may be active at the same time on the same output connection. Outputs and inputs may be mapped to the same external input- output connection with or without the output being controllable for placement into an inactive state, e.g., high impedance or open collector. When the input is required to receive external data over the external input-output connection, the output may be placed into the inactive state.

86. 发明公开

EP1961120A4 METHOD OF PRODUCING AND OPERATING A LOW POWER JUNCTION FIELD EFFECT TRANSISTOR 审中-公开
标题翻译：方法生产和经营的阻隔 - 场效应晶体管低功耗
公开(公告)号：EP1961120A4
公开(公告)日：2008-12-31
申请号：EP06844945
申请日：2006-12-07
申请人： DSM SOLUTIONS INC
发明人： KAPOOR ASHOK KUMAR
IPC分类号： H03K19/0175
CPC分类号： H03K19/0941 , H01L27/098 , H01L29/66901 , H01L29/808 , H03K2217/0018
摘要： A method for using an inverter with a pair of complementary junction field effect transistors (CJFET) with a small linewidth is provided. The method includes having an input capacitance for said CJFET inverter to be less than the corresponding input capacitance of a CMOS inverter of similar linewidth. The CJFET operates at a power supply with a lesser value than the voltage drop across a forward-biased diode having a reduced switching power as compared to said CMOS inverter and having a propagation delay for said CJFET inverter that is at least comparable to the corresponding delay of said CMOS inverter.

87. 发明公开

EP2005591A1 COMMUNICATION CIRCUIT WITH SELECTABLE SIGNAL VOLTAGE 审中-公开
标题翻译：与可选择的电压信号通信电路
公开(公告)号：EP2005591A1
公开(公告)日：2008-12-24
申请号：EP06740542.3
申请日：2006-03-30
申请人： Tte Technology, Inc.
发明人： NOVAK, David
IPC分类号： H03K19/0175
CPC分类号： G06F13/4072
摘要： The disclosed embodiments relate to a communication circuit (100). An exemplary embodiment of the communication circuit (100) comprises a first branch (101, 103) adapted to operate at a first signal voltage level, a first source voltage contact (105) adapted to deliver a voltage corresponding to the first signal voltage level to the first branch (101, 103), a second branch (107, 109) adapted to operate at a second signal voltage level that is higher than the first signal voltage level, a second source voltage contact (111 ) adapted to receive a voltage corresponding to the second signal voltage level via an external connector(136) and to deliver the voltage corresponding to the second signal voltage level to the second branch (107, 109), and a voltage selection circuit (126) coupled to the first source voltage contact (105) and the second source voltage contact (111 ), the voltage selection circuit (126) configured to provide the first signal voltage level to the first branch (101, 103) and the second signal voltage level to the second branch (107, 109).

88. 发明公开

EP1979754A1 ANORDNUNG UND VERFAHREN ZUM UMWANDELN EINES DIGITALEN SIGNALS MIT EINEM HOHEN SPANNUNGSHUB IN EIN DIGITALES SIGNAL MIT EINEM DEMGEGENÜBER KLEINEREN SPANNUNGSHUB 有权转让
标题翻译：装置和方法用于转换为数字信号具有高电压摆幅数字信号以较小的另一方面电压摆幅
公开(公告)号：EP1979754A1
公开(公告)日：2008-10-15
申请号：EP06705906.3
申请日：2006-02-01
申请人： SIEMENS AKTIENGESELLSCHAFT
发明人： GRÖSSLER, Stefan , KAPP, Harald , ULBRICH, Frank
IPC分类号： G01R19/165 , G01R15/22 , H04B10/00 , H03K7/02 , H03K19/0175
CPC分类号： H03K7/02 , H03K19/017545
摘要： The invention relates, inter alia, to an arrangement (10) for converting a first digital signal (Uh) with a first voltage swing into a second digital signal (Un) with a voltage swing which is smaller than the first voltage swing. The invention provides a threshold value detection device (30) which compares an input signal, which is applied to the input and corresponds to the first digital signal or has been formed with the latter, with a threshold value (Uref) and which - if the input signal exceeds the threshold value - generates a pulse sequence (Pl) comprising switch-on and switch-off pulses. A DC isolation device (40) which is connected to the output (A30) of the threshold value detection device (30) forwards the pulse sequence (Pl), with potential isolation, to a signal recovery device (50) which generates the second digital signal using the pulse sequence (P2) which is applied to the signal output (A50) of the DC isolation device.

89. 发明授权

EP1417760B1 CIRCUIT FOR IMPROVING NOISE IMMUNITY BY DV/DT BOOSTING 有权
标题翻译：电路用于改善噪声抗扰度BY DV / DT-BOOSTING
公开(公告)号：EP1417760B1
公开(公告)日：2008-06-25
申请号：EP02742371.4
申请日：2002-07-01
申请人： INTERNATIONAL RECTIFIER CORPORATION
发明人： GRASSO, Massimo, International Rectifier Corp. , SUBARAMANIAN, Muthu
IPC分类号： H03K19/0175
CPC分类号： H03K19/00361
摘要： A circuit for suppressing false operation of a level shift circuit (10) due to a noise transient, the circuit comprising a first transistor (103) coupled to a voltage source (VB) of the level shift circuit and being coupled to pass a current when a noise transient is present on the voltage source and an output terminal (BOOST) coupled to the first transistor providing as an injected signal a current proportional to the current in the first transistor to at least one level shift transistor of the level shift circuit to prevent false triggering of the level shift circuit due to the noise transient.

90. 发明授权

EP0920134B1 Interface circuit 有权
标题翻译：接口电路
公开(公告)号：EP0920134B1
公开(公告)日：2008-04-02
申请号：EP98309680.1
申请日：1998-11-25
申请人： KABUSHIKI KAISHA TOSHIBA
发明人： Endo, Tamotsu , Goushi, Youichi
IPC分类号： H03K19/173 , H03K19/0175
CPC分类号： G06F13/4077

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