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    • 85. 发明公开
    • DISK DRIVE CONTROL APPARATUS
    • 磁盘驱动器控制装置
    • EP0125921A3
    • 1986-12-30
    • EP84303267
    • 1984-05-15
    • DATA GENERAL CORPORATION
    • GERSHENSON, EDWARDLEMONE, LOUIS A.FALETRA, SALVATORE
    • G06F3/06G11B20/10G11B5/09
    • G06F3/0601G06F2003/0692
    • The apparatus allows a single drive to serve two control­ lers which provide control signals on respective buses CBI(1) and CBI(2) (1609 and 1613) including RESERVE and RELEASE instructions. These instructions are applied to respective programmable logic arrays (PLAs 1601, 1603) which also receive signals fed back from state registers (1605, 1607). The registers include bits ERES1, ERES2 which are set when respective RESERVE Instructions are received and ERES2, ERES1 respective = 0, bits IRES1, IRES2 which are set when respective RESERVE instructions are received while ERES2, ERES1 respectively = 1 and INT1, INT2 which are set when ERES1, ERES2 = 1 and ERES2, ERES1 = 0 respectively. INT1 and INT2 send interrupts back to the respectively controllers and a controller which is thus enabled to use the drive does so in a succession of operations involving resetting of INT1, INT2 by a status control instruction from the controller. When the controller is finished it sends the RELEASE instruction to reset ERES1, ERES2 as the case may be. If a controller sends a RESERVE instruction, say on CBI(1), when the other controller is using the drive, i.e. ERES2 = 1, ERES1 is not set but IRES1 is set. When the other controller sends RELEASE and resets ERES2, this reset in conjunction with IRES1 = 1 causes ERES1 to be set. The combination ERES1 = 1 and ERES2 = 0 causes INT1 to be set, as above.
    • 该设备允许单个驱动器服务两个控制器,这两个控制器在包括RESERVE和RELEASE指令的相应总线CBI(1)和CBI(2)(1609和1613)上提供控制信号。 这些指令被应用于也接收从状态寄存器(1605,1607)反馈的信号的相应可编程逻辑阵列(PLA 1601,1603)。 寄存器包括ERES1,ERES2和ERES2,ERES1,ERES2分别在接收到相应RESERVE指令时设置,ERES2,ERES1分别为0,ERES2,ERES1分别接收RESETVE指令时设置的位IRES1,IRES2 = 1,INT1,INT2分别为 当ERES1,ERES2 = 1和ERES2,ERES1 = 0时分别置位。 INT1和INT2将中断发送回相应的控制器,并且因此能够使用该驱动器的控制器通过来自控制器的状态控制指令在涉及INT1,INT2的复位的连续操作中这样做。 控制器完成后,它会发送RELEASE指令以根据具体情况重置ERES1,ERES2。 如果控制器在CBI(1)上发送RESERVE指令,则当另一个控制器正在使用该驱动器时,即ERES2 = 1,ERES1未置位但IRES1置位。 当另一个控制器发送RELEASE并复位ERES2时,该复位与IRES1 = 1一起导致ERES1置位。 如上所述,组合ERES1 = 1和ERES2 = 0将导致INT1置位。
    • 86. 发明公开
    • Disk drive system
    • 磁盘驱动系统
    • EP0126610A3
    • 1986-12-17
    • EP84303268
    • 1984-05-15
    • DATA GENERAL CORPORATION
    • Gershenson, EdwardLemone, Louis A.Faletra, SalvatoreCaldara, StephenLippitt, Mark C.Braun, William A.
    • G06F03/06G11B05/09
    • G06F3/0601G06F2003/0692
    • The system comprises a controller connected to a disk drive or drives by a bus including data lines and various control and handshaking lines. One line effects a CONTROL/DATA selection so that the drive knows whether codes sent on the data lines are disk data or drive control instructions. Another line effects a HEADER/DATA selection to distinguish the header and data portions of a disk sector. The controller includes a microprocessor (1911) with a register (1969) holding an expected header EHDR, a register (1967) holding the number SCOUNT of sectors to be read or written and a register (1965) holding the number of codes in a sector. in a read or write operation a signal CTLIDDCA from a sequencer (1945) select HEADER and a receiver, selected by a sequencer signal DP/INT, puts received codes on to a data bus (1913). The microprocessor (1911) receives sector headers in this way until there is a match, whereupon a signal CSIGS is given to the sequencer (1945) which causes CTL/DDCA to select DATA and DP/INT to enable the data receiver or driver depending upon whether the operation is read or write. The codes are counted down by decrementing DCOUNT. When DCOUNT = 0 (end of sector) SCOUNT is decremented and another signal CSIGS causes the sequencer to revert to the conditions for looking for the next expected header which is calculated by the microprocessor and entered in EHDR. Where SCOUNT reaches 0 the read or write operation is complete.
    • 90. 发明公开
    • Secondary storage facility employing serial communications between drive and controller
    • 设施用于与驱动器和控制单元之间的串行通信后台存储器。
    • EP0077007A2
    • 1983-04-20
    • EP82109213.7
    • 1982-10-05
    • DIGITAL EQUIPMENT CORPORATION
    • Rubinson, Barry L.Gardner, Edward A.Bean, Robert G.Beckman, Michael E.Sergeant, O. WinstonMcLean, Peter T.
    • G06F3/06G06F13/00
    • G06F11/1443G06F3/0601G06F11/0727G06F11/0793G06F13/423G06F2003/0692G06F2003/0697
    • A secondary storage facility employing serial communications between drive (30) and controller (20). A dedicated cable (10) of four conductors is used to connect each controller/drive pair. Each conductor carries one undirectional channel. A first channel (16) is used for command messages and data sent from controller to drive. A second carries response messages and data from drive to controller (14). Third and fourth channels (18 and 12) carry real-time control signals from controller to drive and from drive to controller, respectively, indicative of controller and drive state, for ues in synchronizing and coordinating transmission. Each of the real-time state signals comprises a repeating bit pattern of predetermined pattern length; each bit in the pattern has a predetermined meaning. (Figs. 3, 4)
      A multi-layered protocol is employed for controller- drive communications over the cable. The first level governs the electrical transmission of messages. Framing and data operations occur at a second level. A third level is used for command and response exchanges. The protocol is synchronous and supports variable length, multiple word messages, each bounded by specific beginning and end frames.
      Specific command/response exchanges are identified. One is for communicating from the drive to the controller certain parametric information about the drive, which the controller must know to be able to use the drive. Another enables a host computer to selectively disable and enable the read-time drive state signals, to allow the host computer to determine all paths for accessing each drive with which it can communicate.
      Each drive may employ multiple error recovery techniques; the controller signals the drive to try such techniques in sequence, according to descending a priori probability of success. The controller does not know or need to know the details of the error recovery procedures.
    • 二级存储设备用人驱动器(30)和控制器(20)之间的串行通信。 的四个导体专用电缆(10),用于连接每个控制器/驱动器对。 每个导体携带一个不定向通道。 信道的第一(16)被用于从控制器发送到驱动命令消息和数据。 第二响应携带消息和数据从驱动器到控制器(14)。 第三和第四信道(18和12)进行实时控制信号从控制器到驱动器和从驱动器到控制器,分别指示控制器和驱动状态下,用于同步和协调传输的UE。 每个实时状态信号包括预定图案长度的重复比特模式; 模式中的每个比特具有预定含义。 一种多层协议被用于在电缆控制器驱动器的通信。 第一级辖的消息的电传输。 帧和数据业务发生在第二层。 第三级用于命令和响应的交流。 该协议是同步的,支持可变的长度,多字信息,每条由特定开始帧和结束帧界定。 特定命令/响应交换被识别。 一个是从驱动到变频器控制器某些参数信息,其中,控制器必须知道能够使用的驱动器进行通信。 另一个使主计算机以选择性地禁用和启用所述读时驱动状态信号,以允许主机计算机确定性矿用于访问的每个驱动器可与之进行通信的所有路径。 每个驱动器可以使用多差错恢复技术; 所述控制器信号的驱动器,以尝试在序列搜索技术,gemäß降序成功的先验概率。 控制器不知道或需要知道的错误恢复过程的细节。