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1. 发明公开

EP0074587A3 Frequency-independent, self-clocking encoding technique and apparatus for digital communications 有权
标题翻译：频率独立，自锁定编码技术和数字通信设备
公开(公告)号：EP0074587A3
公开(公告)日：1983-07-27
申请号：EP82108162
申请日：1982-09-03
申请人： DIGITAL EQUIPMENT CORPORATION
发明人： McLean, Peter T. , Sergeant, O. Winston
IPC分类号： H04L03/00 , H04L25/49 , H03K13/24 , H04L07/02 , H03K13/00
CPC分类号： H04L25/4904 , H03M5/18 , H04L25/4925
摘要： A self-clocking encoding technique for synchronous transmission of digital signals, and apparatus therefor. In an exemplary embodiment, the encoding technique utilizes relatively positive and relatively negative pulses of fixed, predetermined duration. For electrical pulses, the point of reference is preferably a zero baseline. At the leading edge LE, of the i th bit cell, the value of the i th bit is encoded as a positive pulse in the case of a logical "1" (e.g., 82A) or a negative pulse (e.g., 82B) in the case of a logical "0" (Step 41, 42A, 428). Further, if the next subsequent (i.e., (i + 1) th bit has the same value, a pulse of the opposite polarity is injected into the i th bit cell after the leading edge pulse (e.g., 82D). Thus, positive and negative pulses alternate and the information content of the encoded signal has no d.c. component; this facilitates a.c. coupling. Further, the encoding technique is bit-rate (i.e., frequency-) independent and usable over a wide range of bit transfer rates. The receiver can synchronously decode the signal if it knows the pulse width; it need not know the sender's transmission rate and indeed, bit transmission rate may even change from one bit cell to the next. For a fiber optic implementation, a non-zero baseline is used. The optical zero output level replaces the electrical negative pulse level, the half-maximum optical output level replaces the electrical zero level and the maximum optical output level replaces the electrically positive pulse.
摘要翻译：一种用于数字信号同步传输的自定时编码技术及其装置。在示例性实施例中，编码技术利用固定的预定持续时间的相对正和负脉冲。对于电脉冲，参考点优选为零基线。在第i个比特单元的前沿LEi，在逻辑“0”的情况下，第i个比特的值被编码为正脉冲，或者在逻辑“0”的情况下被编码为正脉冲。此外，下一个后续（即，第（i + 1）位具有相同的值，相反极性的脉冲（例如，82D）在前沿脉冲之后被注入到第i个位单元中，因此，正和负脉冲编码信号的信息内容没有直流分量，这有助于交流耦合，而且编码技术是比特率（即频率）独立的，可以在宽范围的比特传输速率下使用，接收机可以同步对信号进行解码，如果它知道脉冲宽度，则不需要知道发送方的传输速率，实际上，比特传输速率甚至可能从一个比特单元变为下一个。对于光纤实现，使用非零基准。光学零输出电平取代电负脉冲电平，半最大光输出电平取代电零电平，最大光输出电平取代电正脉冲。

2. 发明公开

EP0077007A2 Secondary storage facility employing serial communications between drive and controller 有权转让
标题翻译：设施用于与驱动器和控制单元之间的串行通信后台存储器。
公开(公告)号：EP0077007A2
公开(公告)日：1983-04-20
申请号：EP82109213.7
申请日：1982-10-05
申请人： DIGITAL EQUIPMENT CORPORATION
发明人： Rubinson, Barry L. , Gardner, Edward A. , Bean, Robert G. , Beckman, Michael E. , Sergeant, O. Winston , McLean, Peter T.
IPC分类号： G06F3/06 , G06F13/00
CPC分类号： G06F11/1443 , G06F3/0601 , G06F11/0727 , G06F11/0793 , G06F13/423 , G06F2003/0692 , G06F2003/0697
摘要： A secondary storage facility employing serial communications between drive (30) and controller (20). A dedicated cable (10) of four conductors is used to connect each controller/drive pair. Each conductor carries one undirectional channel. A first channel (16) is used for command messages and data sent from controller to drive. A second carries response messages and data from drive to controller (14). Third and fourth channels (18 and 12) carry real-time control signals from controller to drive and from drive to controller, respectively, indicative of controller and drive state, for ues in synchronizing and coordinating transmission. Each of the real-time state signals comprises a repeating bit pattern of predetermined pattern length; each bit in the pattern has a predetermined meaning. (Figs. 3, 4)
A multi-layered protocol is employed for controller- drive communications over the cable. The first level governs the electrical transmission of messages. Framing and data operations occur at a second level. A third level is used for command and response exchanges. The protocol is synchronous and supports variable length, multiple word messages, each bounded by specific beginning and end frames.
Specific command/response exchanges are identified. One is for communicating from the drive to the controller certain parametric information about the drive, which the controller must know to be able to use the drive. Another enables a host computer to selectively disable and enable the read-time drive state signals, to allow the host computer to determine all paths for accessing each drive with which it can communicate.
Each drive may employ multiple error recovery techniques; the controller signals the drive to try such techniques in sequence, according to descending a priori probability of success. The controller does not know or need to know the details of the error recovery procedures.
摘要翻译：二级存储设备用人驱动器（30）和控制器（20）之间的串行通信。的四个导体专用电缆（10），用于连接每个控制器/驱动器对。每个导体携带一个不定向通道。信道的第一（16）被用于从控制器发送到驱动命令消息和数据。第二响应携带消息和数据从驱动器到控制器（14）。第三和第四信道（18和12）进行实时控制信号从控制器到驱动器和从驱动器到控制器，分别指示控制器和驱动状态下，用于同步和协调传输的UE。每个实时状态信号包括预定图案长度的重复比特模式; 模式中的每个比特具有预定含义。一种多层协议被用于在电缆控制器驱动器的通信。第一级辖的消息的电传输。帧和数据业务发生在第二层。第三级用于命令和响应的交流。该协议是同步的，支持可变的长度，多字信息，每条由特定开始帧和结束帧界定。特定命令/响应交换被识别。一个是从驱动到变频器控制器某些参数信息，其中，控制器必须知道能够使用的驱动器进行通信。另一个使主计算机以选择性地禁用和启用所述读时驱动状态信号，以允许主机计算机确定性矿用于访问的每个驱动器可与之进行通信的所有路径。每个驱动器可以使用多差错恢复技术; 所述控制器信号的驱动器，以尝试在序列搜索技术，gemäß降序成功的先验概率。控制器不知道或需要知道的错误恢复过程的细节。

3. 发明公开

EP0074587A2 Frequency-independent, self-clocking encoding technique and apparatus for digital communications 有权
标题翻译：常见问题解答，selbsttaktierende Kodierungstechnik und Einrichtungfürdigitale Kommunikation。
公开(公告)号：EP0074587A2
公开(公告)日：1983-03-23
申请号：EP82108162.7
申请日：1982-09-03
申请人： DIGITAL EQUIPMENT CORPORATION
发明人： McLean, Peter T. , Sergeant, O. Winston
IPC分类号： H03M5/00 , H03M5/18 , H03M5/04 , H04L25/49 , H04L7/02
CPC分类号： H04L25/4904 , H03M5/18 , H04L25/4925
摘要： A self-clocking encoding technique for synchronous transmission of digital signals, and apparatus therefor. In an exemplary embodiment, the encoding technique utilizes relatively positive and relatively negative pulses of fixed, predetermined duration. For electrical pulses, the point of reference is preferably a zero baseline. At the leading edge LE, of the i th bit cell, the value of the i th bit is encoded as a positive pulse in the case of a logical "1" (e.g., 82A) or a negative pulse (e.g., 82B) in the case of a logical "0" (Step 41, 42A, 428). Further, if the next subsequent (i.e., (i + 1) th bit has the same value, a pulse of the opposite polarity is injected into the i th bit cell after the leading edge pulse (e.g., 82D). Thus, positive and negative pulses alternate and the information content of the encoded signal has no d.c. component; this facilitates a.c. coupling. Further, the encoding technique is bit-rate (i.e., frequency-) independent and usable over a wide range of bit transfer rates. The receiver can synchronously decode the signal if it knows the pulse width; it need not know the sender's transmission rate and indeed, bit transmission rate may even change from one bit cell to the next.
For a fiber optic implementation, a non-zero baseline is used. The optical zero output level replaces the electrical negative pulse level, the half-maximum optical output level replaces the electrical zero level and the maximum optical output level replaces the electrically positive pulse.
摘要翻译：一种用于数字信号的同步传输的自定时编码技术及其装置。在示例性实施例中，编码技术利用固定的预定持续时间的相对正和负脉冲。对于电脉冲，参考点优选为零基线。在第i个位单元的前沿LEi，在逻辑“0”的情况下，第i位的值被编码为正脉冲，在逻辑“0”的情况下，被编码为正脉冲。此外，下一个后续（即，第（i + 1）位具有相同的值，相反极性的脉冲（例如，82D）在前沿脉冲之后被注入到第i个位单元中，因此，正和负脉冲编码信号的信息内容没有直流分量，这有助于交流耦合，而且编码技术是比特率（即频率）独立的，可以在宽范围的比特传输速率下使用，接收机可以同步如果它知道脉冲宽度，则对信号进行解码;它不需要知道发送器的传输速率，实际上，比特传输速率甚至可能从一个比特单元变为下一个。对于光纤实现，使用非零基线。光学零输出电平取代电负脉冲电平，半最大光输出电平取代电零电平，最大光输出电平取代电正脉冲。

4. 发明授权

EP0077007B1 Secondary storage facility employing serial communications between drive and controller 有权转让
标题翻译：使用驱动器和控制器之间的串行通信的二级存储设备
公开(公告)号：EP0077007B1
公开(公告)日：1988-09-21
申请号：EP82109213.7
申请日：1982-10-05
申请人： DIGITAL EQUIPMENT CORPORATION
发明人： Rubinson, Barry L. , Gardner, Edward A. , Bean, Robert G. , Beckman, Michael E. , Sergeant, O. Winston , McLean, Peter T.
IPC分类号： G06F3/06 , G06F13/00
CPC分类号： G06F11/1443 , G06F3/0601 , G06F11/0727 , G06F11/0793 , G06F13/423 , G06F2003/0692 , G06F2003/0697

5. 发明授权

EP0074587B1 Frequency-independent, self-clocking encoding technique and apparatus for digital communications 有权
标题翻译：频率独立，自锁定编码技术和数字通信设备
公开(公告)号：EP0074587B1
公开(公告)日：1985-12-18
申请号：EP82108162.7
申请日：1982-09-03
申请人： DIGITAL EQUIPMENT CORPORATION
发明人： McLean, Peter T. , Sergeant, O. Winston
IPC分类号： H03M5/00 , H03M5/18 , H03M5/04 , H04L25/49 , H04L7/02
CPC分类号： H04L25/4904 , H03M5/18 , H04L25/4925

6. 发明公开

EP0077007A3 Secondary storage facility employing serial communications between drive and controller 有权转让
标题翻译：使用驱动器和控制器之间的串行通信的二级存储设备
公开(公告)号：EP0077007A3
公开(公告)日：1983-08-31
申请号：EP82109213
申请日：1982-10-05
申请人： DIGITAL EQUIPMENT CORPORATION
发明人： Rubinson, Barry L. , Gardner, Edward A. , Bean, Robert G. , Beckman, Michael E. , Sergeant, O. Winston , McLean, Peter T.
IPC分类号： G06F03/06 , G06F03/04
CPC分类号： G06F11/1443 , G06F3/0601 , G06F11/0727 , G06F11/0793 , G06F13/423 , G06F2003/0692 , G06F2003/0697
摘要： A secondary storage facility employing serial communications between drive (30) and controller (20). A dedicated cable (10) of four conductors is used to connect each controller/drive pair. Each conductor carries one undirectional channel. A first channel (16) is used for command messages and data sent from controller to drive. A second carries response messages and data from drive to controller (14). Third and fourth channels (18 and 12) carry real-time control signals from controller to drive and from drive to controller, respectively, indicative of controller and drive state, for ues in synchronizing and coordinating transmission. Each of the real-time state signals comprises a repeating bit pattern of predetermined pattern length; each bit in the pattern has a predetermined meaning. (Figs. 3, 4) A multi-layered protocol is employed for controller- drive communications over the cable. The first level governs the electrical transmission of messages. Framing and data operations occur at a second level. A third level is used for command and response exchanges. The protocol is synchronous and supports variable length, multiple word messages, each bounded by specific beginning and end frames. Specific command/response exchanges are identified. One is for communicating from the drive to the controller certain parametric information about the drive, which the controller must know to be able to use the drive. Another enables a host computer to selectively disable and enable the read-time drive state signals, to allow the host computer to determine all paths for accessing each drive with which it can communicate. Each drive may employ multiple error recovery techniques; the controller signals the drive to try such techniques in sequence, according to descending a priori probability of success. The controller does not know or need to know the details of the error recovery procedures.

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