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61. 发明授权

EP3053167B1 PHASE HYSTERETIC MAGNETIC JOSEPHSON JUNCTION MEMORY CELL 有权
公开(公告)号：EP3053167B1
公开(公告)日：2020-05-06
申请号：EP14747479.5
申请日：2014-07-16
申请人： Northrop Grumman Systems Corporation
发明人： HERR, Anna Y. , HERR, Quentin P. , NAAMAN, Ofer
IPC分类号： G11C11/16 , G11C11/44 , G01R33/035

62. 发明公开

EP3635726A1 MAGNETIC FLUX CONTROL IN SUPERCONDUCTING DEVICES 无效
公开(公告)号：EP3635726A1
公开(公告)日：2020-04-15
申请号：EP18813336.7
申请日：2018-06-04
申请人： The Regents of the University of California
发明人： MARTINIS, John
IPC分类号： G11C11/44 , H01L39/22

63. 发明公开

EP3573065A1 MEMORY SYSTEM WITH A CONTENT ADDRESSABLE SUPERCONDUCTING MEMORY 审中-公开
公开(公告)号：EP3573065A1
公开(公告)日：2019-11-27
申请号：EP19178578.1
申请日：2017-04-17
申请人： Microsoft Technology Licensing, LLC
发明人： REOHR, William R. , KONIGSBURG, Brian R.
IPC分类号： G11C15/02 , G11C15/04 , G11C15/06 , G11C11/44
摘要： A memory system including a content addressable memory having an array of content addressable memory elements including a plurality of rows of content addressable memory elements and a plurality of columns of content addressable memory elements is provided. Each of the content addressable memory elements further includes a first superconducting quantum interference device (SQUID) and a second superconducting quantum interference device (SQUID), where an input bit to each of the content addressable memory elements is compared with: (1) a first state of the first SQUID and (2) a second state of the second SQUID to generate an output signal. The memory system further includes a Josephson magnetic random access memory (JMRAM), coupled to the content addressable memory.

64. 发明授权

EP2929535B1 RESISTANCE REGLABLE 有权转让
标题翻译：电阻可恢复
公开(公告)号：EP2929535B1
公开(公告)日：2017-09-20
申请号：EP13801586.2
申请日：2013-12-06
申请人： Thales , CNRS (Centre National de la Recherche Scientifique)
发明人： BRIATICO, Javier , VILLEGAS, Javier , BERNARD, Rozenn
IPC分类号： G11C11/22 , G11C11/44 , G11C11/54 , G11C11/56 , G11C13/00 , H01L39/22 , H01L27/18 , H01L45/00 , H01C7/10
CPC分类号： H01C7/10 , G11C11/22 , G11C11/44 , G11C11/54 , G11C11/5657 , G11C13/0002 , G11C2213/52 , H01L39/126 , H01L39/22 , H01L45/04 , H01L45/1233 , H01L45/1253 , H01L45/147

65. 发明授权

EP2707903B1 PHASE QUBIT CELL HAVING ENHANCED COHERENCE 有权
标题翻译：相位QUBIT单元具有增强的相干性
公开(公告)号：EP2707903B1
公开(公告)日：2017-08-09
申请号：EP12799979.5
申请日：2012-06-15
申请人： Northrop Grumman Systems Corporation
发明人： LEWIS, Rupert M. , NAAMAN, Ofer
IPC分类号： H01L29/06 , G11C11/44
CPC分类号： G11C11/44

66. 发明公开

EP2856468A4 JOSEPHSON MAGNETIC MEMORY CELL SYSTEM 有权
标题翻译：约瑟夫森磁存储单元系统
公开(公告)号：EP2856468A4
公开(公告)日：2016-02-24
申请号：EP13796635
申请日：2013-05-14
申请人： NORTHROP GRUMMAN SYSTEMS CORP , UNIV MICHIGAN STATE
发明人： NAAMAN OFER , MILLER DONALD , HERR ANNA Y , BIRGE NORMAN O
IPC分类号： G11C11/16 , G11C11/44 , H01L39/22 , H01L43/08
CPC分类号： G11C11/44 , G11C11/16 , G11C11/1673 , G11C11/1675 , H01L39/223 , H01L43/08
摘要： One aspect of the present invention includes a Josephson magnetic memory system. The system includes a superconducting electrode that conducts a read current. The system also includes a hysteretic magnetic Josephson junction (HMJJ). The HMJJ can store a binary value and convert superconducting pairs associated with the read current flowing through the HMJJ from a singlet-state to a triplet-state. The system further includes a write circuit magnetically coupled to the HMJJ and configured to write the binary value into the at HMJJ in response to at least one write current and a read circuit configured to determine the binary value stored in the HMJJ in response to application of the read current to the HMJJ.

67. 发明公开

EP1745488A2 SPIN BARRIER ENHANCED MAGNETORESISTANCE EFFECT ELEMENT AND MAGNETIC MEMORY USING THE SAME 有权转让
标题翻译：自旋保温扩展了磁阻效应，并使用此SANTANDER磁性存储器元
公开(公告)号：EP1745488A2
公开(公告)日：2007-01-24
申请号：EP05752255.9
申请日：2005-05-11
申请人： Grandis, Inc.
发明人： THIERRY, Valet
IPC分类号： G11C11/44
CPC分类号： H01L43/08 , G11C11/16
摘要： A method and system for providing a magnetic element that is used in a magnetic memory device. The magnetic element includes pinned (122), spacer (13), free (140), and spin barrier layers (150). The spacer layer (130) is nonmagnetic and resides between the pinned (122) and free layers (140). The free layer (140) can be switched using spin transfer when a write current is passed through the magnetic element. The free layer (140) resides between the spacer layer (130) and the spin barrier (150) layer. The spin barrier layer (150) is configured to reduce an outer surface contribution to a damping constant of the free layer (140).

68. 发明授权

EP0280363B1 Circuit de stockage d'informations à faible temps d'accès 失效
标题翻译：信息存储电路低访问时间
公开(公告)号：EP0280363B1
公开(公告)日：1992-10-21
申请号：EP88200281.9
申请日：1988-02-16
申请人： LABORATOIRES D'ELECTRONIQUE PHILIPS , Philips Electronics N.V.
发明人： Gabillard, Bertrand Société Civile S.P.I.D. , Patillon, Jean-Noel Société Civile S.P.I.D.
IPC分类号： G11C11/44
CPC分类号： G11C11/44 , Y10S505/831 , Y10S505/833

69. 发明公开

EP0330743A3 Dynamic random access memory (RAM) 失效
标题翻译：动态随机存取存储器（RAM）
公开(公告)号：EP0330743A3
公开(公告)日：1991-11-06
申请号：EP88120022.4
申请日：1988-11-30
申请人： NEC HOME ELECTRONICS, LTD.
发明人： Ito, Susumu
IPC分类号： G11C11/44 , G11C19/32 , G11C21/00 , H01L27/18
CPC分类号： G11C21/00 , G11C11/44 , G11C19/32 , H01L27/18
摘要： A dynamic RAM (30) comprises: a plurality of superconducting rings (S1...Sn) arranged in a line with the adjacent rings (S1,S2;...;Sn-1,Sn) partially superposed one above another; a driving circuit (12) connected to the superconducting rings (S1...Sn) through an input portion (14); and a detection circuit (18) connected to the rings (S1...Sn) through an output portion (16). In response to a current signal (io) inputted from the driving circuit (12), currents (i1...in)are successively induced in the superconducting rings (S1...Sn) through magnetic flux and detected by the detection circuit (18). Information can be stored by recycling the current signal in a loop including the superconducting rings (S1...Sn).
摘要翻译：动态RAM（30）包括：多个与相邻的环（S1，S2; ...; Sn-1，Sn）成直线排列成一条线的超导环（S1 ... Sn）通过输入部分连接到超导环（S1 ... Sn）的驱动电路（12）; 以及通过输出部分（16）连接到所述环（S1 ... Sn）的检测电路（18）。响应于从驱动电路（12）输入的电流信号（io），电流（i1 ... in）通过磁通量在超导环（S1 ... Sn）中被连续感应并被检测电路 18）。可以通过在包括超导环（S1 ... Sn）的回路中回收当前信号来存储信息。

70. 发明公开

EP0330743A2 Dynamic random access memory (RAM) 失效
标题翻译： Dynamische Schreib / Lese-Speicher。
公开(公告)号：EP0330743A2
公开(公告)日：1989-09-06
申请号：EP88120022.4
申请日：1988-11-30
申请人： NEC HOME ELECTRONICS, LTD.
发明人： Ito, Susumu
IPC分类号： G11C11/44 , G11C19/32 , G11C21/00 , H01L27/18
CPC分类号： G11C21/00 , G11C11/44 , G11C19/32 , H01L27/18
摘要： A dynamic RAM (30) comprises: a plurality of superconducting rings (S1...Sn) arranged in a line with the adjacent rings (S1,S2;...;Sn-1,Sn) partially superposed one above another; a driving circuit (12) connected to the superconducting rings (S1...Sn) through an input portion (14); and a detection circuit (18) connected to the rings (S1...Sn) through an output portion (16). In response to a current signal (io) inputted from the driving circuit (12), currents (i1...in)are successively induced in the superconducting rings (S1...Sn) through magnetic flux and detected by the detection circuit (18). Information can be stored by recycling the current signal in a loop including the superconducting rings (S1...Sn).
摘要翻译：动态RAM（30）包括：多个与相邻的环（S1，S2; ...; Sn-1，Sn）成直线排列成一条线的超导环（S1 ... Sn）通过输入部分连接到超导环（S1 ... Sn）的驱动电路（12）; 以及通过输出部分（16）连接到所述环（S1 ... Sn）的检测电路（18）。响应于从驱动电路（12）输入的电流信号（io），电流（i1 ... in）通过磁通量在超导环（S1 ... Sn）中被连续感应并被检测电路 18）。可以通过在包括超导环（S1 ... Sn）的回路中回收当前信号来存储信息。

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