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1. 发明公开

EP3266024A1 TIMING CONTROL IN A QUANTUM MEMORY SYSTEM 有权
标题翻译：量子存储系统中的时序控制
公开(公告)号：EP3266024A1
公开(公告)日：2018-01-10
申请号：EP16711404.0
申请日：2016-02-26
申请人： Northrop Grumman Systems Corporation
发明人： REOHR, William Robert , SHAUCK, Steven Brian , MILLER, Donald Lynn , HORNER, Jeremy William , JOSEPHSEN, Nathan Trent
IPC分类号： G11C11/44 , G11C7/22 , G11C7/12 , H01F6/00 , G11C8/04 , G11C8/18 , H01L39/22
CPC分类号： G11C11/44 , B82Y10/00 , B82Y20/00 , B82Y25/00 , G11C7/12 , G11C7/22 , G11C8/04 , G11C8/18 , G11C11/16 , G11C11/1655 , G11C11/1657 , G11C11/1659 , G11C11/1693 , G11C19/32
摘要： One embodiment describes a quantum memory system. The system includes a plurality of quantum memory cells arranged in an array of rows and columns. Each of the plurality of quantum memory cells can be configured to store a binary logic state in response to write currents in a write operation and configured to provide an indication of the binary logic state in response to read currents in a read operation. The system also includes an array controller comprising a plurality of flux pumps configured to provide the write currents and the read currents with respect to the rows and columns. The array controller can be configured to control timing associated with the write operation and the read operation in response to memory request signals based on application of the write currents and the read currents and based on recharging flux associated with the plurality of flux pumps.

2. 发明公开

EP3192176A1 GROUND GRID FOR SUPERCONDUCTING CIRCUITS 有权
标题翻译：超导电路的地面栅格
公开(公告)号：EP3192176A1
公开(公告)日：2017-07-19
申请号：EP14846777.2
申请日：2014-09-10
申请人： Northrop Grumman Systems Corporation
发明人： HERR, Quentin P. , HERR, Anna Y. , SHAUCK, Steven Brian , MIN, Eileen Jiwon
IPC分类号： H03K19/195 , H01L39/22 , H01L39/24
CPC分类号： H01L27/18 , G11C11/44 , G11C19/32 , H01L39/025 , H01L39/22 , H01L39/223 , H01L39/24 , H03K19/195
摘要： One example includes a superconducting circuit. The circuit includes a plurality of layers comprising a first conductor layer and a second conductor layer overlying the first conductor layer, each of the first and second conductor layers comprising at least one signal element. The circuit also includes a ground grid that is conductively coupled to ground and comprises a first plurality of parallel ground lines that occupy the first conductor layer and extend in a first direction and a second plurality of parallel ground lines that occupy the second conductor layer and extend in a second direction that is orthogonal with respect to the first direction.
摘要翻译：一个例子包括超导电路。该电路包括多个层，该多个层包括第一导体层和覆盖第一导体层的第二导体层，第一和第二导体层中的每一个包括至少一个信号元件。该电路还包括导电地耦合到地的接地网格，并且包括占据第一导体层并且在第一方向上延伸的第一多个平行的接地线和占据第二导体层并延伸的第二多个平行的接地线在相对于第一方向正交的第二方向上。

3. 发明公开

EP0330743A3 Dynamic random access memory (RAM) 失效
标题翻译：动态随机存取存储器（RAM）
公开(公告)号：EP0330743A3
公开(公告)日：1991-11-06
申请号：EP88120022.4
申请日：1988-11-30
申请人： NEC HOME ELECTRONICS, LTD.
发明人： Ito, Susumu
IPC分类号： G11C11/44 , G11C19/32 , G11C21/00 , H01L27/18
CPC分类号： G11C21/00 , G11C11/44 , G11C19/32 , H01L27/18
摘要： A dynamic RAM (30) comprises: a plurality of superconducting rings (S1...Sn) arranged in a line with the adjacent rings (S1,S2;...;Sn-1,Sn) partially superposed one above another; a driving circuit (12) connected to the superconducting rings (S1...Sn) through an input portion (14); and a detection circuit (18) connected to the rings (S1...Sn) through an output portion (16). In response to a current signal (io) inputted from the driving circuit (12), currents (i1...in)are successively induced in the superconducting rings (S1...Sn) through magnetic flux and detected by the detection circuit (18). Information can be stored by recycling the current signal in a loop including the superconducting rings (S1...Sn).
摘要翻译：动态RAM（30）包括：多个与相邻的环（S1，S2; ...; Sn-1，Sn）成直线排列成一条线的超导环（S1 ... Sn）通过输入部分连接到超导环（S1 ... Sn）的驱动电路（12）; 以及通过输出部分（16）连接到所述环（S1 ... Sn）的检测电路（18）。响应于从驱动电路（12）输入的电流信号（io），电流（i1 ... in）通过磁通量在超导环（S1 ... Sn）中被连续感应并被检测电路 18）。可以通过在包括超导环（S1 ... Sn）的回路中回收当前信号来存储信息。

4. 发明公开

EP0330743A2 Dynamic random access memory (RAM) 失效
标题翻译： Dynamische Schreib / Lese-Speicher。
公开(公告)号：EP0330743A2
公开(公告)日：1989-09-06
申请号：EP88120022.4
申请日：1988-11-30
申请人： NEC HOME ELECTRONICS, LTD.
发明人： Ito, Susumu
IPC分类号： G11C11/44 , G11C19/32 , G11C21/00 , H01L27/18
CPC分类号： G11C21/00 , G11C11/44 , G11C19/32 , H01L27/18
摘要： A dynamic RAM (30) comprises: a plurality of superconducting rings (S1...Sn) arranged in a line with the adjacent rings (S1,S2;...;Sn-1,Sn) partially superposed one above another; a driving circuit (12) connected to the superconducting rings (S1...Sn) through an input portion (14); and a detection circuit (18) connected to the rings (S1...Sn) through an output portion (16). In response to a current signal (io) inputted from the driving circuit (12), currents (i1...in)are successively induced in the superconducting rings (S1...Sn) through magnetic flux and detected by the detection circuit (18). Information can be stored by recycling the current signal in a loop including the superconducting rings (S1...Sn).
摘要翻译：动态RAM（30）包括：多个与相邻的环（S1，S2; ...; Sn-1，Sn）成直线排列成一条线的超导环（S1 ... Sn）通过输入部分连接到超导环（S1 ... Sn）的驱动电路（12）; 以及通过输出部分（16）连接到所述环（S1 ... Sn）的检测电路（18）。响应于从驱动电路（12）输入的电流信号（io），电流（i1 ... in）通过磁通量在超导环（S1 ... Sn）中被连续感应并被检测电路 18）。可以通过在包括超导环（S1 ... Sn）的回路中回收当前信号来存储信息。

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