专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

61. 发明公开

EP0553744A2 Signal delay method, signal delay device and circuit for use in the apparatus 失效
标题翻译：一种用于信号延迟器件和电路，用于在所述装置中使用的信号延迟处理。
公开(公告)号：EP0553744A2
公开(公告)日：1993-08-04
申请号：EP93101077.1
申请日：1993-01-25
申请人： KONICA CORPORATION
发明人： Takaki, Kouichi, Konica Corporation , Azumai, Mitsuo, Konica Corporation , Ishii, Hiroshi, Konica Corporation
IPC分类号： H03K5/135
CPC分类号： H03K5/131 , H03K5/135 , H03K2005/00234
摘要： In a circuit provided in a single integrated circuit unit for use in a signal delay device, there is provided with a device in which an input signal is delayed and a plurality of delay signals, each having a different delay period from the input signal, are outputted, and a detector in which a delay signal having a specific relation with the input signal among the plurality of delay signals is detected.
摘要翻译：在单个集成电路单元提供了一种用于在一个信号延迟装置的电路，提供了一种具有在其中输入信号的装置被延迟和延迟信号的复数，每个都具有从所述输入信号的不同的延迟时间，是在其中检测具有延迟信号的多元性之间的输入信号的特定关系的延迟信号的输出，以及检测器。

62. 发明公开

EP0513330A1 CIRCUIT DE GENERATION D'IMPULSIONS DE LARGEUR VARIABLE POUR UN DRIVER D'AFFICHAGE A CRISTAUX LIQUIDES 失效
标题翻译：与脉冲宽度可变的液晶显示器的驱动器脉冲产生电路。
公开(公告)号：EP0513330A1
公开(公告)日：1992-11-19
申请号：EP92901728.0
申请日：1991-12-03
申请人： THOMSON S.A.
发明人： BRIGGS, George, Roland , STEWART, Roger, Green
IPC分类号： G09G3 , H03K5 , H03K7 , H03M1
CPC分类号： H03K7/08 , H03K5/131 , H03K5/135 , H03K2005/00195
摘要： Générateur d'impulsions de largeur variable comprenant un ensemble d'états logiques, lesquels sont raccordés en cascade. Chaque étage est disposé de manière à recevoir l'un d'un ensemble de signaux d'horloge de phase différente et répondant à l'un des bits d'un mot binaire définissant la largeur de l'impulsion. Tous les étages sont initialement désactivés par une impulsion de précharge survenant au commencement de chaque intervalle d'impulsion variable. Les étages successifs sont activés par une impulsion d'horloge sélectionnée par l'étage précédent. Le tout dernier étage fournit une sortie correspondant à une impulsion de largeur variable.

63. 发明公开

EP0455294A3 Self-aligning sampling system and logic analyser comprising a number of such sampling systems 失效
标题翻译：自适应采样系统和包含多个采样系统的逻辑分析仪
公开(公告)号：EP0455294A3
公开(公告)日：1991-11-13
申请号：EP91200990.9
申请日：1991-04-25
申请人： FLUKE CORPORATION
发明人： Lankreijer,Willem
IPC分类号： G06F11/22 , H03K5/135
CPC分类号： H03K5/135 , G06F11/25
摘要： A self-aligning sampling system is proposed for sampling digital signals, for example in a logic analyser. The sampling system comprises an adjustable delay line with tapping points for clock signals. In conjunction with the system clock, the further clock signals are used to take several samples of the digital signal in a time slot of the system clock. In order to achieve equidistant sampling even in the case of a large process spread in elementary delay units of the delay line, the delay line is calibrated. The system clock is then connected to the data input and expressed in elementary delay units on the basis of measurement. Subsequently, the delay line between clock signal tapping points is adjusted on the basis thereof.

64. 发明公开

EP0453083A1 An asynchronous delay circuit 失效
标题翻译： AsynchroneVerzögerungsschaltung。
公开(公告)号：EP0453083A1
公开(公告)日：1991-10-23
申请号：EP91302029.3
申请日：1991-03-11
申请人： MOTOROLA, INC.
发明人： Parsi, Kaveh , Harnishfeger, David B.
IPC分类号： H03K5/135
CPC分类号： H03K5/135
摘要： A circuit for asynchronously delaying an input signal whereby the precision of the time delay is proportional to the precision of the clock. A first circuit (12) is coupled across a first capacitor (16) for charging the first capacitor to a predetermined voltage when the clock is in a first logic state and discharging the first capacitor when the clock is in a second logic state. A peak-hold circuit (20) having an input coupled to a first terminal of the first capacitor and an output signal at an output that provides a reference voltage representative of the peak voltage occurring at the input of the peak-hold circuit which is a function of the time interval the clock occupied the first logic state. A second circuit (30) is coupled across a second capacitor (26) for charging the second capacitor when the input signal is in a first logic state, and discharging the second capacitor when the input signal is in a second logic state. Also, a comparator (24) having a first input coupled to the output of the peak-hold circuit, a second input coupled to a first terminal of the second capacitor, and an output at which an output signal is provided that represents the input signal delayed by a predetermined time which is a function of the reference voltage.
摘要翻译：用于异步延迟输入信号的电路，由此时间延迟的精度与时钟的精度成正比。第一电路（12）跨越第一电容器（16）耦合，用于当时钟处于第一逻辑状态时将第一电容器充电至预定电压，并且当时钟处于第二逻辑状态时，第一电路（12）被放电。具有耦合到第一电容器的第一端子的输入端和输出端处的输出信号的峰值保持电路（20），其提供表示在峰值保持电路的输入处出现的峰值电压的参考电压，该峰值电压为时钟占用第一个逻辑状态的时间间隔的功能。当输入信号处于第一逻辑状态时，第二电路（30）跨越第二电容器（26）耦合，用于对第二电容器充电，并且当输入信号处于第二逻辑状态时，第二电路（30）放电第二电容器。此外，具有耦合到峰值保持电路的输出的第一输入端的比较器（24），耦合到第二电容器的第一端子的第二输入端和提供表示输入信号的输出信号的输出端延迟了作为参考电压的函数的预定时间。

65. 发明公开

EP0415047A2 Precision timing circuit 失效
标题翻译： Präzisionszeitschaltung。
公开(公告)号：EP0415047A2
公开(公告)日：1991-03-06
申请号：EP90113404.9
申请日：1990-07-13
申请人： International Business Machines Corporation
发明人： Woyke, Justin Alden , Bula, Orest , Koch, Garrett Stephen , Gomez, Richard Santiago
IPC分类号： H03K5/135
CPC分类号： H03K5/135
摘要： The present disclosure describes a clock circuit, together with a control current generator (11) and a ratio circuit (12) coupled thereto. The ratio circuit, of the invention, utilizes at least two capacitors (C1, C2) each of which is coupled in series with a respective transistor and arranged in parallel with one another. Each capacitor transistor pair is in parallel to the other and coupled between the control current generator and ground so that at least one of the transistors in a selected capacitor transistor series can be selectively turned off while the other can be directly controlled by the clock cycle.
The present invention is thus a circuit, for generating timing edges within a clock cycle which timing edges can be any fraction of the clock cycle, which comprises a clock, a controlled current generator, and a ratio circuit coupled to the clock and the generator. The preferred embodiment of this invention comprises at least two capacitor-transistor pairs coupled in parallel between the generator and ground with the clock being coupled to the control electrode of one of the transistors and being coupled to the control electrode of the other transistor together with a turn-off signal source. Means (Q3, Q4) for discharging the capacitors are included in the circuit.
摘要翻译：本公开描述了与控制电流发生器（11）和耦合到其的比率电路（12）一起的时钟电路。本发明的比率电路利用至少两个电容器（C1，C2），每个电容器与相应的晶体管串联耦合并彼此并联布置。每个电容晶体管对彼此并联并耦合在控制电流发生器和接地之间，使得所选择的电容器晶体管串联中的至少一个晶体管可以选择性地截止，而另一个可以由时钟周期直接控制。因此，本发明是用于在时钟周期内产生定时边沿的电路，其中定时边缘可以是时钟周期的任何分数，其包括时钟，受控电流发生器和耦合到时钟和发生器的比率电路。本发明的优选实施例包括在发生器和地之间并联耦合的至少两个电容 - 晶体管对，其中时钟耦合到晶体管之一的控制电极，并连接到另一个晶体管的控制电极以及关闭信号源。用于放电电容器的装置（Q3，Q4）包括在电路中。

66. 发明授权

EP0216113B1 Synchronisierungseinrichtung 失效
标题翻译：同步设备
公开(公告)号：EP0216113B1
公开(公告)日：1990-10-31
申请号：EP86111270.4
申请日：1986-08-14
申请人： SIEMENS AKTIENGESELLSCHAFT
发明人： Spengler, Werner, Dr.rer.nat. , Kranabetter, Johann, Dipl.-Ing.
IPC分类号： G11B20/16 , G11B5/012 , G11B27/10 , G11B20/10 , H03K5/135
CPC分类号： H03K5/135 , G11B5/012 , G11B20/10 , G11B20/16 , G11B27/10

67. 发明公开

EP0319184A1 Two stage synchronizer 失效
标题翻译： Zweistufige Synchronisiereinrichtung。
公开(公告)号：EP0319184A1
公开(公告)日：1989-06-07
申请号：EP88310990.2
申请日：1988-11-21
申请人： TANDEM COMPUTERS INCORPORATED
发明人： Sanner,Martin W.
IPC分类号： H03K5/135
CPC分类号： H03K5/135
摘要： A method, and apparatus to implement that method, for synchronizing an incoming signal to the transitions of a digital clock signal in the form of a periodic pulse train. The apparatus includes a first circuit pair of flip-flops arranged to sample and store the state of the input signal on either the positive and negative transitions of the periodic pulse train, and OR gate producing a signal indicative of the stored content of the first circuit, and a third circuit that samples and stores the first signal at each transition of the periodic pulse train to produce therefrom a representation of the input signal synchronized to one of the transitions of the pulse train.
摘要翻译：一种实现该方法的方法和装置，用于使输入信号与周期性脉冲串形式的数字时钟信号的转换同步。该装置包括第一电路对触发器，其布置成在周期性脉冲串的正向和反向转换上采样和存储输入信号的状态，以及OR门产生指示第一电路的存储内容的信号以及第三电路，其在周期性脉冲串的每个转变处对第一信号进行采样和存储，从而产生与脉冲串的一个转换同步的输入信号的表示。

68. 发明公开

EP0272653A3 Synchronizing circuit 失效
标题翻译：同步电路
公开(公告)号：EP0272653A3
公开(公告)日：1989-03-08
申请号：EP87118866.0
申请日：1987-12-18
申请人： KABUSHIKI KAISHA TOSHIBA
发明人： Okubo, Yasuo Patent Division , Hirasawa, Masataka Patent Division
IPC分类号： H03K5/135
CPC分类号： H03K5/135
摘要： A pulse signal transfer control circuit (TC) is located between an input pulse detecting circuit (11, 12, 13, 14) for detecting the arrival of an externally applied input pulse and outputting an pulse signal with a predetermined pulse width, and an R-S flip-flop (15). The transfer control circuit (TC) prohibits the pulse signal from being transferred to the R-S flip-flop (15) during a period in which the R-S flip-flop (15) is set, a period of generation of a first internal clock signal, and a period of generation of a second internal clock signal, and allows the pulse signal to be transferred to the first R-S flip-flop (15) during period in which the first and second clock signals are not generated and the period in which the first R-S flip-flop (15) is reset.
摘要翻译：脉冲信号传输控制电路（TC）位于用于检测外部施加的输入脉冲的到达并输出具有预定脉冲宽度的脉冲信号的输入脉冲检测电路（11,12,13,14）和RS 触发器（15）。传输控制电路（TC）在RS触发器（15）置位的时段期间禁止脉冲信号传输到RS触发器（15），产生第一内部时钟信号的时段，和产生第二内部时钟信号的周期，并且允许脉冲信号在没有产生第一和第二时钟信号的周期期间将第一RS触发器（15）传送到第一RS触发器 RS触发器（15）复位。

69. 发明公开

EP0272653A2 Synchronizing circuit 失效
标题翻译： Synchronisationsschaltung。
公开(公告)号：EP0272653A2
公开(公告)日：1988-06-29
申请号：EP87118866.0
申请日：1987-12-18
申请人： KABUSHIKI KAISHA TOSHIBA
发明人： Okubo, Yasuo Patent Division , Hirasawa, Masataka Patent Division
IPC分类号： H03K5/135
CPC分类号： H03K5/135
摘要： A pulse signal transfer control circuit (TC) is located between an input pulse detecting circuit (11, 12, 13, 14) for detecting the arrival of an externally applied input pulse and outputting an pulse signal with a predetermined pulse width, and an R-S flip-flop (15). The transfer control circuit (TC) prohibits the pulse signal from being transferred to the R-S flip-flop (15) during a period in which the R-S flip-flop (15) is set, a period of generation of a first internal clock signal, and a period of generation of a second internal clock signal, and allows the pulse signal to be transferred to the first R-S flip-flop (15) during period in which the first and second clock signals are not generated and the period in which the first R-S flip-flop (15) is reset.
摘要翻译：脉冲信号传送控制电路（TC）位于输入脉冲检测电路（11,12,13,14）之间，用于检测外部施加的输入脉冲的到达并输出预定脉冲宽度的脉冲信号，RS 触发器（15）。传输控制电路（TC）禁止在设置RS触发器（15）的时段期间将脉冲信号传送到RS触发器（15），产生第一内部时钟信号的周期，以及产生第二内部时钟信号的周期，并且允许在不产生第一和第二时钟信号的时段期间将脉冲信号传送到第一RS触发器（15），并且在第一 RS触发器（15）被复位。

70. 发明公开

EP0202085A2 Self-checking, dual railed, leading edge synchronizer 失效
标题翻译： SelbstprüfenderZweikanal-Anstiegsflanken-Synchronisierer。
公开(公告)号：EP0202085A2
公开(公告)日：1986-11-20
申请号：EP86303561.4
申请日：1986-05-09
申请人： TANDEM COMPUTERS INCORPORATED
发明人： Chandran, Srikumar R. , Walker, Mark S.
IPC分类号： H03K5/135 , G06F1/04
CPC分类号： H03K5/151 , G06F1/12 , H03K5/135 , H04L7/0045
摘要： The present invention relates to a digital logic circuit and method for synchronizing the leading edges of a skewed true-complement signal pair. The circuit of the present invention is comprised of two similar, interconnected circuit halves, each of which includes three D flip-flop stages. The outputs from the second D flip-flop stages from the two circuit halves are applied to the two inputs of two identical logic gates, such that the signal pair is synchronously transmitted to a pair of output gates through a third D flip-flop stage in each circuit half. The second D flip-flop stages also prevent metastable states from reaching the synchronizer output. Metastable states may result if the input setup time is violated for the first D flip-flop stages. The third D flip-flop stage in each circuit half also eliminates any signal irregularities generated in the logic circuitry from appearing on the synchronizer output lines. The present invention is self-checking in that any single fault in the input signals or in the synchronizer circuit itself will result in the synchronizer output pair not having a true complement relationship.
摘要翻译：本发明涉及一种数字逻辑电路和方法，用于使偏斜的真互补信号对的前沿同步。本发明的电路由两个相似的互连电路半部组成，每个电路包括三个D触发器级。来自两个电路半部的来自第二D触发器级的输出被施加到两个相同逻辑门的两个输入端，使得信号对通过第三D触发器级同步地传输到一对输出门，每个电路一半。第二个D触发器级还可以防止亚稳态到达同步器输出。如果第一个D触发器级的输入建立时间被违反，则可能导致转换状态。每个电路半中的第三个D触发器级也消除了在同步器输出线上出现的逻辑电路中产生的任何信号不规则。本发明是自检，因为输入信号或同步器电路本身中的任何单一故障将导致同步器输出对不具有真实的补码关系。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式