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1. 发明授权

EP0771491B1 VERY LOW NOISE, WIDE FREQUENCY RANGE PHASE LOCK LOOP 失效
标题翻译： PHAZENREGELKREIS大面积频率和非常低的噪声
公开(公告)号：EP0771491B1
公开(公告)日：2001-05-02
申请号：EP96920258.9
申请日：1996-05-16
申请人： VLSI TECHNOLOGY, INC.
发明人： BHUSHAN, Bharat , ARCUS, Christopher, A. , TA, Paul, D.
IPC分类号： H03K3/0231 , H03L7/099
CPC分类号： H03L7/0995 , H03K3/0231 , H03K3/0322
摘要： A ring-style, multi-stage VCO of a phase lock loop circuit (100) includes two or more differential amplifier stages. The phase lock loop (100) includes a lowpass filter (108) connected between a control voltage terminal and a voltage-to-current converter stage (110), which includes a first source-follower MOS transistor M1 with a source resistor R1 and a second diode-connected MOS transistor M2 connected to its drain terminal. A differential amplifier stage includes a current-source MOS transistor M10 having a gate terminal connected to the drain of the first MOS transistor M1 to current mirror the drain current of M1. The differential amplifier stage also includes a pair of MOS transistors M4 and M5 connected to the drain terminal of the current-source MOS transistor M10. The gate terminal of MOS transistor M4 is an IN terminal and the gate terminal of MOS transistor M5 is an IN_ terminal. The drain terminal of MOS transistor M4 provides an OUT_ signal for the differential amplifier stage and the drain terminal of MOS transistor M5 provides an OUT signal for the differential amplifier stage. A MOS transistor M6 forms a load impedance for MOS transistor M4 and a MOS transistor M7 forms a load impedance for MOS transistor M5. The gate terminals of M6 and M7 are connected to the voltage control input terminal of the phase lock loop.

2. 发明公开

EP0862116A3 A smart debug interface circuit 失效
标题翻译：接口电路的故障排除
公开(公告)号：EP0862116A3
公开(公告)日：2000-01-05
申请号：EP98300075.3
申请日：1998-01-07
申请人： VLSI TECHNOLOGY, INC.
发明人： Ponte, Christian
IPC分类号： G06F11/267 , G06F11/00
CPC分类号： G06F11/3656 , G01R31/31705 , G01R31/318583 , G06F11/261
摘要： The present invention comprises a smart debug interface circuit (203) for the diagnostic testing and debugging of a software application for a programmable digital processor system. The smart debug interface circuit (203) of the present invention includes an instruction register (404) for coupling to an instruction bus of a programmable digital processor (202). The instruction register (404) is adapted to drive instructions onto the instruction bus. The instruction register (404) couples to the instruction bus in a parallel manner. The smart debug interface circuit (203) of the present invention includes a data register (407) for coupling to a data bus of the programmable digital processor (202). The data register (407) is adapted to read data from the data bus and couples to the data bus in a parallel manner. The instruction register (404) and data register (407) are each coupled to an interface port. The interface port couples the smart debug interface circuit to a host computer system. A control logic circuit (401) is also included in the smart debug interface circuit (203) of the present invention. The control logic circuit (401) is coupled to the instruction register (404), the data register (407), and the interface port. The control logic circuit (401) interfaces a debugging program on the host computer system to the programmable digital processor (202). Additionally, the control logic circuit (401) interfaces the debugging program with the programmable digital processor (202) without imposing boundary scan bus delay on the instruction bus or the data bus.

3. 发明公开

EP0946016A2 Synchronization device and method 审中-公开
标题翻译： Synchronisationsvorrichtung und Verfahren
公开(公告)号：EP0946016A2
公开(公告)日：1999-09-29
申请号：EP99302234.2
申请日：1999-03-23
申请人： VLSI TECHNOLOGY, INC.
发明人： Ott, Stefan
IPC分类号： H04L7/02 , H03L7/07 , H03L7/095
CPC分类号： H03L7/199 , H03L7/095 , H04L7/0012
摘要： A clock synchronization circuit for synchronizing a first communications device and a second communications device to enable digital communication between the devices. The clock synchronization circuit includes an oscillator circuit adapted to generate a base clock signal. A first frequency divider is coupled to the oscillator circuit. The first frequency divider generates a first divider clock signal from the base clock signal. A phase comparison circuit is coupled to receive the first divider clock signal. Additionally, the phase comparison circuit is also coupled to the oscillator circuit to control the frequency of the base clock signal. The phase comparison circuit receives a reference clock signal from a first communications device and adjusts the base clock frequency to correct a phase difference between the first divider clock signal and the reference clock signal. The clock synchronization circuit further includes a second frequency divider coupled to the oscillator circuit. The second frequency divider is adapted to generate a second divider clock signal from the base clock signal, wherein the second divider clock signal varies in response to the correcting performed on the base clock signal by the phase comparison circuit. The second frequency divider subsequently provides the second divider clock signal to a second communications device such that the first communications device and the second communications device are synchronized.
摘要翻译：一种用于同步第一通信设备和第二通信设备以实现设备之间的数字通信的时钟同步电路。时钟同步电路包括适于产生基本时钟信号的振荡器电路。第一分频器耦合到振荡器电路。第一分频器从基本时钟信号产生第一分频器时钟信号。相位比较电路被耦合以接收第一分频器时钟信号。此外，相位比较电路还耦合到振荡器电路以控制基本时钟信号的频率。相位比较电路从第一通信设备接收参考时钟信号，并且调整基本时钟频率以校正第一分频器时钟信号和参考时钟信号之间的相位差。时钟同步电路还包括耦合到振荡器电路的第二分频器。第二分频器适于从基本时钟信号产生第二分频器时钟信号，其中第二分频器时钟信号响应于由相位比较电路对基准时钟信号执行的校正而变化。第二分频器随后将第二分频器时钟信号提供给第二通信设备，使得第一通信设备和第二通信设备同步。

4. 发明公开

EP0860781A2 Multiple interface connection device and method for reconfiguring standard PC-card interface 失效
标题翻译： Mehrschnittstellenkupplungsvorrichtung und Verfahren zum Rekonfigurieren von Standard-PC-Kartenschnittstellen
公开(公告)号：EP0860781A2
公开(公告)日：1998-08-26
申请号：EP98301275.8
申请日：1998-02-20
申请人： VLSI TECHNOLOGY, INC.
发明人： Junghans, Andreas , Pletl, Josef E.
IPC分类号： G06F13/40
CPC分类号： G06F13/4068
摘要： An apparatus and method which overcomes connectivity limitations on PCMCIA and PC-CARD95 compatible devices by reconfiguring standard PCMCIA and PC-CARD pins for additional electrical interfaces. A detection circuit in the PC-card can detect the different interfaces. Once the different interfaces are identified, the connections to the receptacles of the PC-card connector are reconfigured such that the functional assignments of the receptacles conform with the requirements of each different interface. Thus, connection between different electrical interfaces to the physical interface of a PCMCIA-compatible device, without interference between them is possible. This eliminates the need for extra connectors other than the standard PCMCIA and PC-CARD95 connector. Thus, more versatile products with enhanced connectivity may be designed which use the PCMCIA and PC-CARD95 standards.
摘要翻译：一种通过重新配置标准PCMCIA和PC-CARD引脚以实现其他电接口来克服PCMCIA和PC-CARD95兼容设备的连接限制的设备和方法。 PC卡中的检测电路可以检测不同的接口。一旦识别了不同的接口，则重新配置到PC卡连接器的插座的连接，使得插座的功能分配符合每个不同接口的要求。因此，不同电接口与PCMCIA兼容设备的物理接口之间的连接是不可能的。这不需要额外的连接器，而不是标准PCMCIA和PC-CARD95连接器。因此，可以设计具有增强连接性的更通用的产品，其使用PCMCIA和PC-CARD95标准。

5. 发明公开

EP0834823A1 Method and apparatus for efficiently implementing complex function blocks in integrated circuit designs 失效
标题翻译：用于在集成电路中的高效实现复杂的功能部分的方法和装置
公开(公告)号：EP0834823A1
公开(公告)日：1998-04-08
申请号：EP97114554.5
申请日：1997-08-22
申请人： VLSI TECHNOLOGY, INC.
发明人： Dockser, Kenneth A. , Ehmann, Gregory E.
IPC分类号： G06F17/50
CPC分类号： G06F17/5045
摘要： A method in accordance with the present invention for developing an integrated circuit design using a compilation tool includes: (A) developing at least one HDL template by: (a) creating the HDL template; (b) creating a parameter file and a parameter check file for the HDL template; and (c) encrypting the HDL template; (B) developing design specifications for use in creating HDL for synthesis and for use in compiling one or more macro blocks; (C) creating the HDL for synthesis; and (D) creating netlists for at least one macro block instantiated in the HDL template using the design specifications. A development tool of the present invention implements the method on a computer system to form a portion of an integrated circuit fabrication system.
摘要翻译：在雅舞蹈与用于使用编译工具的集成电路设计开发本发明的方法包括：（A）显影由至少一个HDL模板：（a）创建的HDL模板; （B）创建的参数文件和用于HDL模板参数检查文件; 和（c）加密HDL模板; （B）显影设计规范以用于在编译一个或多个宏块创建HDL用于合成和使用; （C）产生用于合成的HDL; 和（D）用于在使用设计书中的HDL模板实例化至少一个宏块创建的网表。本发明的开发工具实现了一个计算机系统上的方法，以形成集成电路制造系统的一部分。

6. 发明公开

EP0804803A1 BARRIER ENHANCEMENT AT THE SIALICIDE LAYER 失效
标题翻译： BARRIER增加自对准硅化物层
公开(公告)号：EP0804803A1
公开(公告)日：1997-11-05
申请号：EP94929856.0
申请日：1994-09-22
申请人： VLSI TECHNOLOGY, INC.
发明人： BRUGGE, Hunter, B.
IPC分类号： H01L21 , H01L23
CPC分类号： H01L21/28518 , H01L23/485 , H01L23/53223 , H01L2924/0002 , Y10S438/952 , H01L2924/00
摘要： A first metallic layer (16) is deposited over the substrate (10) and the contact well (14) formed therein. The first metallic layer (16) is then exposed to a gas to allow the gas to stuff the first metallic layer, thereby improving the barrier characteristics of the first metallic layer. A second metallic layer (22) is deposited over the first stuffed metallic layer (16). A third metallic layer (24) is then deposited over the second metallic layer. An anti-reflective fourth layer of metal (26) is then deposited over the third metallic layer (24). The exposure of the first metallic layer (16) to a gas and all of the metal layer deposition steps are performed in a low-pressure environment. Also, as an result of subsequent processing steps required in the formation of semiconductor devices, the portions of the first metallic layer which are present outside of the contact well are removed. The remaining portion of the first metallic layer forms a self-aligned silicide within the contact well.

7. 发明公开

EP0802652A2 Data encryptor having a scalable clock 失效
标题翻译：具有可缩放时钟数据加密装置
公开(公告)号：EP0802652A2
公开(公告)日：1997-10-22
申请号：EP97302548.9
申请日：1997-04-15
申请人： VLSI TECHNOLOGY, INC.
发明人： Buer,Mark L.
IPC分类号： H04L9/00
CPC分类号： H04L9/0625 , H04L9/0637 , H04L2209/12
摘要： A method for encrypting and decrypting digital data. The digital data is initially latched by an input register. Sixteen separate cipher stages cascaded in series are used to encrypt the digital data. These cipher stages are operating at a maximum frequency limited only by the process technology. The encoded digital data from the last cipher stage is stored in an output register. The input and output registers are capable of being clocked at an interface frequency that is different from that of the DES core's data frequency. After an appropriate number of cycles have elapsed, the output register is sampled. A programmable counter is used to indicate when the output register contains valid encrypted data.

8. 发明公开

EP0771490A1 LOW NOISE, LOW VOLTAGE PHASE LOCK LOOP 失效
标题翻译：低噪音低电压阶段LOOP
公开(公告)号：EP0771490A1
公开(公告)日：1997-05-07
申请号：EP96914667.0
申请日：1996-05-16
申请人： VLSI TECHNOLOGY, INC. , Arcus, Christopher A. , Bhushan, Bharat , Ta, Paul D.
发明人： ARCUS, Christopher, A. , BHUSHAN, Bharat , TA, Paul, D.
IPC分类号： H03K3 , H03L7
CPC分类号： H03L7/0995 , H03K3/0231 , H03K3/0322
摘要： A ring-style, multi-stage VCO of a phase lock loop circuit (100) includes two or more differential amplifier stages (132-140). The phase lock loop (100) includes a lowpass filter (108) connected between a control voltage terminal and a voltage-to-current converter stage (110), which includes a first source-follower MOS transistor M1 with a source resistor R1 and a diode-connected MOS transistor M2 connected to its drain terminal. A current-source MOS transistor M8 has a gate terminal connected to the drain of the first MOS transistor M1 such that the transistor M8 mirrors current of transistor M1. A diode-connected transistor M9 has its gate terminal and its drain terminal connected together and also to the drain terminal of transistor M8. A differential amplifier stage includes a current-source MOS transistor M10 having a gate terminal connected to the drain of the first MOS transistor M1 to mirror the drain current of M1. The differential amplifier stage also includes a pair of MOS transistors M4 and M5 connected to the drain terminal of the current-source MOS transistor M10. The gate terminal of MOS transistor M4 is an IN terminal and the gate terminal of MOS transistor M5 is an IN-terminal. The drain terminal of MOS transistor M4 provides an OUT- signal for the differential amplifier stage and the drain terminal of MOS transistor M5 provides an OUT signal for the differential amplifier stage. A MOS transistor M6 forms a load impedance for MOS transistor M4 and a MOS transistor M7 forms a load impedance for MOS transistor M5. The gate terminals of M6 and M7 are connected to the drain terminal of transistor M9.

9. 发明公开

EP0734587A1 THIN CAVITY DOWN BALL GRID ARRAY PACKAGE BASED ON WIREBOND TECHNOLOGY 失效
标题翻译： DÜNNESMITKAVITÄTNACH UNTEN GERICHTETESKUGELMATRIXGEHÄUSEBASIERND AUF DRAHTBANDIERUNGS-TECHNOLOGIE
公开(公告)号：EP0734587A1
公开(公告)日：1996-10-02
申请号：EP94931885.0
申请日：1994-10-17
申请人： VLSI TECHNOLOGY, INC.
发明人： MASSINGILL, Thomas, J.
IPC分类号： H01L23 , H01L21
CPC分类号： H01L23/49816 , H01L23/13 , H01L23/142 , H01L24/48 , H01L24/49 , H01L24/73 , H01L2224/32245 , H01L2224/48091 , H01L2224/49175 , H01L2224/49433 , H01L2224/73265 , H01L2924/00014 , H01L2924/01006 , H01L2924/01014 , H01L2924/01027 , H01L2924/01029 , H01L2924/01079 , H01L2924/014 , H01L2924/10253 , H01L2924/14 , H01L2924/15153 , H01L2924/15165 , H01L2924/1517 , H01L2924/15311 , H01L2924/1532 , H01L2924/181 , H01L2924/3025 , H01L2924/00 , H01L2224/48227 , H01L2924/00012 , H01L2224/45099 , H01L2224/05599
摘要： A high performance ball grid array is disclosed in which a ball grid array is modified to include a body having a recessed central cavity. The inclusion of a central cavity allows the die to be mounted on the same side of the package in which the solder balls are located. Since the die is mounted on the same side as that of the solder balls, only one set of leads is needed to electrically connect the die to the solder balls, thus requiring only one layer of electrically conductive material within the package, as opposed to conventional ball grid array packages which required two metal layers. In addition, since only one metal layer is needed, the present invention is able to operate without the use of electrically conductive vias. The die is connected via wirebonds to bonding areas located on the package. Each of the bonding areas is substantially co-planar, and each bonding area is located at a different distance from one edge of the central cavity, thereby forming a staggered arrangement. The advantage of positioning the bonding areas in a staggered arrangement is that it enables the spacing between each of the adjacent bonding wires to be maintained, thereby avoiding fan-out of the bonding wires and avoiding the need for multi-level bonding areas in the package.
摘要翻译：公开了一种高性能球栅阵列，其中球栅阵列被修改为包括具有凹陷中心腔的主体。包括中心腔允许模具安装在焊球所在的封装的同一侧。由于芯片安装在与焊球相同的一侧，所以只需要一组引线将裸片与焊球电连接，因此与封装中只需要一层导电材料，这与传统的需要两个金属层的球栅阵列封装。此外，由于仅需要一个金属层，所以本发明能够在不使用导电通孔的情况下工作。管芯通过引线接合连接到位于封装上的接合区域。结合区域中的每一个基本上是共面的，并且每个结合区域位于与中心空腔的一个边缘不同的距离处，从而形成交错排列。以交错布置的方式定位接合区域的优点是能够保持每个相邻的接合线之间的间隔，从而避免了接合线的扇出，并且避免了对封装中的多层结合区域的需要。

10. 发明授权

EP0597015B1 ANTI-FUSE STRUCTURES AND METHODS FOR MAKING SAME 失效
标题翻译：反熔丝结构和工艺及其
公开(公告)号：EP0597015B1
公开(公告)日：1996-06-19
申请号：EP92917139.5
申请日：1992-07-24
申请人： VLSI TECHNOLOGY, INC.
发明人： BOARDMAN, William, J. , CHAN, David, P.-Kwan , CHANG, Kuang-Yeh , GABRIEL, Calvin, T. , JAIN, Vivek , NARIANI, Subhash, R.
IPC分类号： H01L23/525
CPC分类号： H01L21/76888 , H01L23/5252 , H01L2924/0002 , Y10S148/055 , H01L2924/00
摘要： An anti-fuse structure characterized by a substrate (18), an oxide layer (46) formed over the substrate having an opening (48) formed therein, an amorphous silicon material (52) disposed within the opening and contacting the substrate, a conductive protective material (59), such as titanium tungsten, disposed over the amorphous silicon material, and oxide spacers (64) lining the walls of a recess formed within the protective material. The protective material and the spacers provide tighter programming voltage distribution for the anti-fuse structure and help prevent anti-fuse failure.

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