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61. 发明公开

EP0257952A3 Apparatus for detecting and classifying errors in control words 失效
标题翻译：控制字错误检测和分类
公开(公告)号：EP0257952A3
公开(公告)日：1990-01-17
申请号：EP87307261.5
申请日：1987-08-17
申请人： AMDAHL CORPORATION
发明人： Goldman, Gary S. , Semmelmeyer, Mark W.
IPC分类号： G06F11/00 , G06F9/38
CPC分类号： G06F9/3865 , G06F9/3863 , G06F9/3867 , G06F11/0721 , G06F11/0751 , G06F11/0763 , G06F11/10
摘要： In a data processing machine that generates a control word and that includes a plurality of registers connected to receive respective copies of the control word for execution in sections of the data processing machine, the present invention provides an apparatus for detecting an error condition in the execution of the control word. The apparatus detects an error in any of the respective copies of the control word. Further, a second means, responsive to the one copy of the control word in one register, is included for analyzing the one copy to identify a class of possible errors. Finally, responsive to the detection of an error in any of the respective copies and to the class of possible errors, a signal is generated indicating an error condition.

62. 发明授权

EP0111776B1 Interrupt processor 失效
标题翻译：中断处理器
公开(公告)号：EP0111776B1
公开(公告)日：1989-07-19
申请号：EP83111763.5
申请日：1983-11-24
申请人： International Business Machines Corporation
发明人： Sproul, William W. III
IPC分类号： G06F9/38
CPC分类号： G06F9/3865 , G06F9/3863

63. 发明公开

EP0322117A2 Multiprocessor digital data processing system 失效
标题翻译： Multiprozessor-Digitaldatenverarbeitungssystem。
公开(公告)号：EP0322117A2
公开(公告)日：1989-06-28
申请号：EP88311139.5
申请日：1988-11-24
申请人： KENDALL SQUARE RESEARCH CORPORATION
发明人： Frank, Steven J. , Burkhardt, III Henry , Lee, Linda Q. , Goodman, Nathan , Margulies, Benson I. , Weber, Frederick D.
IPC分类号： G06F15/16 , G06F12/08
CPC分类号： G06F9/5016 , G06F9/30003 , G06F9/3004 , G06F9/30047 , G06F9/3005 , G06F9/30087 , G06F9/383 , G06F9/3836 , G06F9/3851 , G06F9/3855 , G06F9/3857 , G06F9/3861 , G06F9/3865 , G06F9/468 , G06F9/52 , G06F11/004 , G06F11/0724 , G06F11/073 , G06F11/0766 , G06F11/0772 , G06F12/0811 , G06F12/0813 , G06F12/0817 , G06F12/0833 , G06F12/10 , G06F12/1018 , G06F12/126 , G06F2212/272 , H04L12/4637 , H04L45/04
摘要： A multiprocessor digital data processing system comprises a plurality of processing cells (18A to 18R, 34A to 34F, 38A, 38B) arranged in a hierarchy of rings (12A to 12F, 14A and 14B, 16). The system selectively allocates storage and moves exclusive data copies from cell to cell in response to access requests generated by the cells. Routing elements are employed to selectively broadcast data access requests, updates and transfers on the rings.
摘要翻译：一种多处理器数字数据处理系统，包括多个处理单元（18A至18R，34A至34F，38A，38B），它们分布在环（12A至12F，14A和14B，16）中。系统选择性地分配存储并且响应于由单元产生的访问请求而将排他数据副本从单元移动到单元。采用路由元素来选择性地广播环上的数据访问请求，更新和传输。

64. 发明授权

EP0155275B1 PREFETCH VALIDATION 失效
标题翻译：预先验证
公开(公告)号：EP0155275B1
公开(公告)日：1989-04-05
申请号：EP84902973.1
申请日：1984-07-16
申请人： MOTOROLA, INC.
发明人： ZOLNOWSKY, John , CRUDELE, Lester, M. , SPAK, Michael, E.
IPC分类号： G06F9/38
CPC分类号： G06F9/30149 , G06F9/3816 , G06F9/3865
摘要： A data processing system comprising an instruction execution unit (2), an n-stage pipeline (14, 16, 17) for providing data segments representing instruction words from a memory (6) to the instruction execution unit (2); means for prefetching instruction words (8) to be executed subsequently to a presently executing instruction and for verifying the validity (20, 22) of the prefetched instruction word prior to execution thereof by the instruction execution unit, and means for causing the instruction execution unit to defer to a fault condition when and only when execution of an invalid instruction is begun.

65. 发明公开

EP0155275A4 PREFETCH VALIDATION. 失效
标题翻译： VORAUSHOLBESTÄTIGUNG。
公开(公告)号：EP0155275A4
公开(公告)日：1986-04-15
申请号：EP84902973
申请日：1984-07-16
申请人： MOTOROLA INC
发明人： ZOLNOWSKY JOHN , CRUDELE LESTER M , SPAK MICHAEL E
IPC分类号： G06F9/30 , G06F9/32 , G06F9/38
CPC分类号： G06F9/30149 , G06F9/3816 , G06F9/3865
摘要： A data processing system comprising an instruction execution unit (2), an n-stage pipeline (14, 16, 17) for providing data segments representing instruction words from a memory (6) to the instruction execution unit (2); means for prefetching instruction words (8) to be executed subsequently to a presently executing instruction and for verifying the validity (20, 22) of the prefetched instruction word prior to execution thereof by the instruction execution unit, and means for causing the instruction execution unit to defer to a fault condition when and only when execution of an invalid instruction is begun.
摘要翻译：一种数据处理系统，包括指令执行单元（2），用于将表示来自存储器（6）的指令字的数据段提供给指令执行单元（2）的n级流水线（14,16,17）;其中，用于预取要在当前执行的指令之后执行的指令字（8）和用于在由指令执行单元执行之前验证预取指令字的有效性（20,22）的装置，以及用于使指令执行单元当且仅当开始执行无效指令时才推迟到故障状态。

66. 发明公开

EP0111776A2 Interrupt processor 失效
标题翻译：中断处理部。
公开(公告)号：EP0111776A2
公开(公告)日：1984-06-27
申请号：EP83111763.5
申请日：1983-11-24
申请人： International Business Machines Corporation
发明人： Sproul, William W. III
IPC分类号： G06F9/38
CPC分类号： G06F9/3865 , G06F9/3863
摘要： An interrupt processor is disclosed for an instruction pipelined digital processor, which includes an instruction classification system with a logic class decoder, a multistage, pipelined, interruptible-sequence detector, a multistage variable-return-address generator, and an active instruction completion, suppression, and termination control, to enable interrupting a sequence of instructions which execute out-of-order in the pipelined and digital processor, and to enable allowing a subsequent return to the interrupted program to resume processing of that program without error.

67. 发明公开

EP3060979A4 PROCESSOR AND METHODS FOR IMMEDIATE HANDLING AND FLAG HANDLING 有权转让
标题翻译： PROZESSOR UND VERFAHREN ZUR SOFORTIGEN MARKIERUNGSHANDHABUNG
公开(公告)号：EP3060979A4
公开(公告)日：2017-07-05
申请号：EP14855674
申请日：2014-10-24
申请人： ADVANCED MICRO DEVICES INC
发明人： VENKATACHAR ASHOK , PUNUKOLLU KARTHIK , AREKAPUDI SRIKANTH , CHITNIS SAMIR A , TALPES EMIL
IPC分类号： G06F9/06
CPC分类号： G06F9/384 , G06F9/30094 , G06F9/30098 , G06F9/30167 , G06F9/3838 , G06F9/3863 , G06F9/3865
摘要： Described herein are methods and processors for flag renaming in groups to eliminate dependencies of instructions. Decoder and execution units in the processor may be configured to rename flags into groups that allow each group to be treated separately as appropriate. This flag renaming eliminates flag dependencies with respect to instructions. This allows an instruction to write exactly the flags that the instruction wants without having to create merge dependencies. Methods and processors are provided for handling immediate values embedded in instructions. A 16 bit immediate bus and a 4 bit encoding/control bus are added at the interface between decode and execution units. For an 8 or 12 bit immediate, the upper 4 bits of the immediate bus contain the encoding bits. For a 16 bit immediate, the encoding/control bus contains the encoding bits. The encoding/control bus indicates when to look at the top four bits of the immediate bus.
摘要翻译：这里描述的是用于组中的标志重命名以消除指令的依赖性的方法和处理器。处理器中的解码器和执行单元可以被配置为将标志重命名为组，从而允许每个组适当分开处理。该标志重命名消除了关于指令的标志依赖性。这允许指令精确地写入指令想要的标志而不必创建合并依赖关系。提供方法和处理器用于处理指令中嵌入的即时值。解码和执行单元之间的接口增加了一个16位立即总线和一个4位编码/控制总线。对于立即数8或12位，立即总线的高4位包含编码位。对于16位立即数，编码/控制总线包含编码位。编码/控制总线指示何时查看直接总线的前四位。

68. 发明公开

EP2972842A1 PROGRAMMABLE CPU REGISTER HARDWARE CONTEXT SWAP MECHANISM 有权
标题翻译： SWAP机制的可编程CPU寄存器的硬件上下文
公开(公告)号：EP2972842A1
公开(公告)日：2016-01-20
申请号：EP14716090.7
申请日：2014-03-07
申请人： Microchip Technology Incorporated
发明人： CATHERWOOD, Michael, I. , KRIS, Bryan , MICKEY, David , KANELLOPOULOS, Joseph
IPC分类号： G06F9/46
CPC分类号： G06F9/30145 , G06F9/3009 , G06F9/3865 , G06F9/462
摘要： A central processing unit (CPU) having an interrupt unit for interrupting execution of instructions, a plurality context defining register sets, wherein each set of registers having the same number of CPU registers, a switching unit for coupling a selected register set within the CPU, wherein the switching unit switches to a predetermined register set of the plurality of context defining register sets upon occurrence of an exception, and a control register configured to control selection of a register set of the plurality of context defining register initiated by an instruction and further operable to indicate a currently used context.

69. 发明授权

EP2093661B1 Generation and use of status flags in a data processor 有权转让
标题翻译：埃及数据公司的Erzeugung und Benutzung von Zustandsflaggen
公开(公告)号：EP2093661B1
公开(公告)日：2015-10-07
申请号：EP09250343.2
申请日：2009-02-11
申请人： Renesas Electronics Corporation
发明人： Arakawa, Fumio
IPC分类号： G06F9/30 , G06F9/302 , G06F9/318 , G06F9/32
CPC分类号： G06F9/30185 , G06F9/3001 , G06F9/30029 , G06F9/30058 , G06F9/30094 , G06F9/3016 , G06F9/30181 , G06F9/3865
摘要： The RISC data processor is based on the idea that in case that there are many flag-generating instructions, the number of flags generated by each instruction is increased so that a decrease of flag-generating instructions exceeds an increase of flag-using instructions in quantity, thereby achieving the decrease in instructions. With the data processor, an instruction for generating flags according to operands' data sizes is defined. To an instruction set handled by the RISC data processor, an instruction capable of executing an operation on operand in more than one data size, which performs a process identical to an operation process conducted on the small-size operand on low-order bits of the large-size operand, and generates flags capable of coping with the respective data sizes regardless of the data size of each operand subjected to the operation is added. Thus, the reduction in instruction code space of the RISC data processor tight in instruction code space can be achieved.
摘要翻译： RISC数据处理器基于以下思想：在存在许多标志生成指令的情况下，由每个指令产生的标志数量增加，使得标志生成指令的减少超过了使用量的指令数量的增加，从而实现指令的减少。使用数据处理器，定义了根据操作数的数据大小生成标志的指令。对于由RISC数据处理器处理的指令集，指令能够执行对多于一个数据大小的操作数的操作，该指令执行与在低位上的小规模操作数上进行的操作处理相同的处理并且生成能够应对各个数据大小的标志，而不管添加了经过操作的每个操作数的数据大小。因此，可以实现RISC数据处理器在指令代码空间中紧缩的指令代码空间的减少。

70. 发明授权

EP0815507B1 STRUCTURE AND METHOD FOR HIGH-PERFORMANCE SPECULATIVE EXECUTION PROCESSOR PROVIDING SPECIAL FEATURES 失效
标题翻译：结构与方法投机命令执行和特殊功能高性能处理器
公开(公告)号：EP0815507B1
公开(公告)日：2013-06-12
申请号：EP96906404.7
申请日：1996-02-13
申请人： FUJITSU LIMITED
发明人： SHEN, Gene, W. , SZETO, John , PATKAR, Niteen, A. , SHEBANOW, Michael, C. , OSONE, Hideki , SIMONE, Michael, A. , MARUYAMA, Takumi
IPC分类号： G06F9/38
CPC分类号： G06F9/3865 , G06F9/3836 , G06F9/384 , G06F9/3842 , G06F9/3855 , G06F9/3857 , G06F9/3859 , G06F9/3863
摘要： A high-performance processor, such as a central processing unit (CPU) (51), that includes structure and methods for providing numerous special processor features and capabilities is disclosed. These structures and methods include, but are not limited to, structure and methods for: (1) aggressively scheduling long latency instructions including load/store instructions while maintaining precise state; maintaining and restoring precise state at any instruction boundary; (2) tracking instruction status to maintain precise state; (3) checkpointing instructions to maintain precise state; (4) creating, maintaining, and using a time-out checkpoint; (5) tracking floating-point exceptions; (6) creating, maintaining, and using a renamable trap-stack; (7) creating, maintaining, and using a Watchpoint for plural simultaneous unresolved branch evaluation; (8) tracking instruction status to maintain precise state; and (9) increasing processor throughput while maintaining precise state.

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