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61. 发明公开

EP2843551A3 Multi-core synchronization mechanism 有权
标题翻译： Mehrkern-Synchronisationsmechanismus
公开(公告)号：EP2843551A3
公开(公告)日：2016-05-04
申请号：EP14179296.0
申请日：2014-07-31
申请人： VIA Technologies, Inc.
发明人： Henry, G. Glenn , Parks, Terry
IPC分类号： G06F9/52
CPC分类号： G06F1/3287 , G06F1/04 , G06F1/32 , G06F9/522 , G06F12/0891 , G06F2212/1028 , G06F2212/60
摘要： A microprocessor includes a control unit configured to selectively control a respective clock signal to each of a plurality of processing cores. Each of the processing cores is configured to separately write a value to the control unit. For each core of the plurality of processing cores, the control unit is configured to turn off the respective clock signal to the core in response to the core writing a value to the control unit. The control unit is configured to detect a condition has occurred when all of the processing cores have written a value to the control unit and the control unit has turned off the respective clock signal to all of the processing cores. The control unit is configured to simultaneously turn on the respective clock signal to all of the processing cores in response to detecting the condition has occurred.

62. 发明授权

EP2508978B1 Microprocessor that performs x86 ISA and ARM ISA machine language program instructions by hardware translation 有权
标题翻译：微处理器通过硬件进行翻译86 ISA和ARM ISA机器语言程序指令
公开(公告)号：EP2508978B1
公开(公告)日：2015-12-30
申请号：EP11185755.3
申请日：2011-10-19
申请人： VIA Technologies, Inc.
发明人： Henry, G. Glenn , Parks, Terry , Hooker, Rodney E.
IPC分类号： G06F9/30
CPC分类号： G06F9/441 , G06F9/265 , G06F9/30043 , G06F9/30072 , G06F9/30076 , G06F9/30105 , G06F9/30123 , G06F9/30145 , G06F9/3017 , G06F9/30174 , G06F9/30189 , G06F9/30196 , G06F9/3802 , G06F9/4401 , G06F9/4403 , G06F15/82

63. 发明公开

EP2950222A2 Dynamically configurable system based on cloud-collaborative experimentation 审中-公开
标题翻译： Dynamisch konfigurierbares System auf Basis von kollaborativen Cloud-Experimenten
公开(公告)号：EP2950222A2
公开(公告)日：2015-12-02
申请号：EP14190886.3
申请日：2014-10-29
申请人： VIA Technologies, Inc.
发明人： Chen, Wen-Chi , Hooker, Rodney E
IPC分类号： G06F15/177
CPC分类号： G06F9/44505 , G06F9/448 , G06F15/177
摘要： A system includes functional units that are dynamically configurable during operation of the system. The system also includes a first module that collects performance data while the system executes a program with the functional units configured according to a configuration setting. The system also includes a second module that sends information to a server. The information includes the performance data, the configuration setting and data from which the program may be identified. The system also includes a third module that instructs the system to reconfigure the functional units with a new configuration setting received from the server while the program is being executed by the system. The new configuration setting is based on analysis by the server of the information sent by the system and of similar information sent by other systems that include the dynamically configurable functional units.
摘要翻译：系统包括在系统运行期间可动态配置的功能单元。系统还包括在系统执行程序时收集性能数据的第一模块，功能单元根据配置设置进行配置。系统还包括向服务器发送信息的第二个模块。该信息包括性能数据，配置设置和可以识别程序的数据。该系统还包括第三模块，其指示系统在由系统执行程序时从服务器接收到的新配置设置来重新配置功能单元。新的配置设置是基于服务器分析系统发送的信息以及其他系统发送的类似信息，包括动态配置的功能单元。

64. 发明公开

EP2840508A3 Apparatus and method for extended cache correction 有权
标题翻译：装置和方法补正缓存扩展
公开(公告)号：EP2840508A3
公开(公告)日：2015-09-02
申请号：EP13193571.0
申请日：2013-11-19
申请人： VIA Technologies, Inc.
发明人： Henry, G. Glenn , Jain, Dinesh K.
IPC分类号： G06F15/76 , G06F9/445 , G06F11/08 , G11C29/00
CPC分类号： G06F12/0802 , G06F3/0619 , G06F3/0632 , G06F3/0673 , G06F11/1008 , G06F15/76 , G11C29/787 , G11C29/802
摘要： An apparatus includes a semiconductor fuse array, a cache memory, and a plurality of cores. The semiconductor fuse array is disposed on a die, into which is programmed the configuration data. The semiconductor fuse array has a first plurality of semiconductor fuses that is configured to store compressed cache correction data. The a cache memory is disposed on the die. The plurality of cores is disposed on the die, where each of the plurality of cores is coupled to the semiconductor fuse array and the cache memory, and is configured to access the semiconductor fuse array upon power-up/reset, to decompress the compressed cache correction data, and to distribute decompressed cached correction data to initialize the cache memory.

65. 发明公开

EP2874092A1 Recurrent BIOS verification with embedded encrypted hash 有权
标题翻译： WiederkehrendePrüfungBIOS mit eingebettetenverschlüsseltenHash
公开(公告)号：EP2874092A1
公开(公告)日：2015-05-20
申请号：EP13197621.9
申请日：2013-12-17
申请人： VIA Technologies, Inc.
发明人： Henry, G Glenn
IPC分类号： G06F21/57
CPC分类号： G06F21/572 , G06F2221/2139
摘要： An apparatus including a ROM and a microprocessor. The ROM includes BIOS contents that are stored as plaintext and an encrypted digest. The encrypted digest includes an encrypted version of a first digest corresponding to the BIOS contents. The microprocessor is coupled to the BIOS ROM, and includes a tamper timer and a tamper detector. The tamper timer periodically generates an interrupt at a prescribed interval. The tamper detector accesses the BIOS contents and the encrypted digest upon assertion of the interrupt, and directs the microprocessor to generate a second digest corresponding to the BIOS contents and a decrypted digest corresponding to the encrypted digest using the same algorithms and key that were employed to generate the first digest and the encrypted digest, and compares the second digest with the decrypted digest, and precludes operation of the microprocessor if the second digest and the decrypted digest are not equal.
摘要翻译：一种包括ROM和微处理器的装置。 ROM包括存储为明文和加密摘要的BIOS内容。加密摘要包括对应于BIOS内容的第一摘要的加密版本。微处理器耦合到BIOS ROM，并且包括篡改定时器和篡改检测器。篡改定时器以规定的间隔周期性地产生中断。篡改检测器在断言时访问BIOS内容和加密摘要，并引导微处理器使用与使用相同的算法和密钥生成对应于BIOS内容的第二摘要和对应于加密摘要的解密摘要生成第一个摘要和加密的摘要，并将第二个摘要与解密的摘要进行比较，如果第二个摘要和解密的摘要不相等，则排除微处理器的操作。

66. 发明公开

EP2843550A2 Dynamic reconfiguration of mulit-core processor 有权
标题翻译： Dynamische Neukonfiguration von Mehrkernprozessoren
公开(公告)号：EP2843550A2
公开(公告)日：2015-03-04
申请号：EP14179294.5
申请日：2014-07-31
申请人： VIA Technologies, Inc.
发明人： Henry, G. Glenn , Parks, Terry , Gaskins, Darius D. , Gaskins, Stephan , Hooker, Rodney E. , Bean, Brent
IPC分类号： G06F9/52
CPC分类号： G06F9/52 , G06F9/522
摘要： A microprocessor includes a plurality of processing cores and a configuration register configured to indicate whether each of the plurality of processing cores is enabled or disabled. Each enabled one of the plurality of processing cores is configured to read the configuration register in a first instance to determine which of the plurality of processing cores is enabled or disabled and generate a respective configuration-related value based on the read of the configuration register in the first instance. The configuration register is updated to indicate that a previously enabled one of the plurality of processing cores is disabled. Each enabled one of the plurality of processing cores is configured to read the configuration register in a second instance to determine which of the plurality of processing cores is enabled or disabled and generate the respective configuration-related value based on the read of the configuration register in the second instance.
摘要翻译：微处理器包括多个处理核心和配置寄存器，配置寄存器被配置为指示多个处理核心中的每一个是启用还是禁用。所述多个处理核心中的每个使能的一个被配置为在第一情况下读取配置寄存器，以确定多个处理核心中的哪一个被启用或禁用，并且基于对配置寄存器的读取生成相应的配置相关值一审。更新配置寄存器以指示多个处理核心中先前启用的一个处理核心被禁用。多个处理核心中的每一个使能的一个被配置为在第二实例中读取配置寄存器，以确定多个处理核心中的哪一个被启用或禁用，并且基于对配置寄存器的读取生成相应的配置相关值第二例。

67. 发明公开

EP2840508A2 Apparatus and method for extended cache correction 有权
标题翻译：扩展高速缓存校正的装置和方法
公开(公告)号：EP2840508A2
公开(公告)日：2015-02-25
申请号：EP13193571.0
申请日：2013-11-19
申请人： VIA Technologies, Inc.
发明人： Henry, G. Glenn , Jain, Dinesh K.
IPC分类号： G06F15/76 , G06F9/445 , G06F11/08
CPC分类号： G06F12/0802 , G06F3/0619 , G06F3/0632 , G06F3/0673 , G06F11/1008 , G06F15/76 , G11C29/787 , G11C29/802
摘要： An apparatus includes a semiconductor fuse array, a cache memory, and a plurality of cores. The semiconductor fuse array is disposed on a die, into which is programmed the configuration data. The semiconductor fuse array has a first plurality of semiconductor fuses that is configured to store compressed cache correction data. The a cache memory is disposed on the die. The plurality of cores is disposed on the die, where each of the plurality of cores is coupled to the semiconductor fuse array and the cache memory, and is configured to access the semiconductor fuse array upon power-up/reset, to decompress the compressed cache correction data, and to distribute decompressed cached correction data to initialize the cache memory.
摘要翻译：一种装置包括半导体熔丝阵列，高速缓冲存储器和多个核心。半导体熔丝阵列设置在管芯上，其中编程有配置数据。半导体熔丝阵列具有被配置为存储压缩的高速缓存校正数据的第一多个半导体熔丝。高速缓冲存储器设置在管芯上。多个核心设置在管芯上，其中多个核心中的每一个耦合到半导体熔丝阵列和高速缓冲存储器，并且被配置为在加电/复位时访问半导体熔丝阵列以解压缩压缩的高速缓存校正数据，并分配解压缩的高速缓存校正数据以初始化高速缓存存储器。

68. 发明公开

EP2811652A1 Digital power gating with global voltage shift 有权
标题翻译： Digitale Stromtorschaltung mit globaler Spannungsverschiebung
公开(公告)号：EP2811652A1
公开(公告)日：2014-12-10
申请号：EP14166643.8
申请日：2014-04-30
申请人： VIA Technologies, Inc.
发明人： Lundberg, James
IPC分类号： H03K19/00 , G06F1/32
CPC分类号： H03K3/012 , G06F1/26 , G06F1/3243 , H03K19/0008 , Y02D10/152
摘要： A system which may be implemented on an integrated circuit including a global supply bus, a gated supply bus, a functional circuit receiving voltage from the gated supply bus, and a digital power gating system. The digital power gating system includes gating devices, a power gating control system, and a global control adjuster. The gating devices are coupled between the global and gated supply buses and are controlled by a digital control value. The power gating control system performs power gating by successively adjusting the digital control value to reduce a voltage of the gated supply bus to a state retention voltage level. The global control adjuster performs a global adjustment of the digital control value to increase the voltage of the gated supply bus to prevent it from falling below the state retention voltage level in response to an impending change of a voltage of the global supply bus.
摘要翻译：可以在包括全局电源总线，门控电源总线，从门控电源总线接收电压的功能电路和数字电源门控系统的集成电路上实现的系统。数字电源门控系统包括门控设备，电源门控控制系统和全局控制调节器。门控设备耦合在全局和门控供电总线之间，并由数字控制值控制。电力门控控制系统通过连续调整数字控制值来执行电力门控，以将门控电源总线的电压降低到状态保持电压电平。全局控制调节器执行数字控制值的全局调整，以增加门控电源总线的电压，以防止其响应于全局电源总线的电压即将发生变化而降低到状态保持电压电平以下。

69. 发明公开

EP2806354A1 Microprocesser that fuses if-then instructions 有权
标题翻译： Mikroprozessor，der Wenn-Dann-Befehle verschmelzt
公开(公告)号：EP2806354A1
公开(公告)日：2014-11-26
申请号：EP13197622.7
申请日：2013-12-17
申请人： VIA Technologies, Inc.
发明人： Parks, Terry , Henry, G Glenn
IPC分类号： G06F9/30
CPC分类号： G06F9/30145 , G06F9/30058 , G06F9/30072 , G06F9/3017 , G06F9/30174 , G06F9/3836
摘要： A microprocessor includes an instruction translation unit that extracts condition information from the IT instruction and fuses the IT instruction with the first IT block instruction. For each instruction of the IT block, the instruction translation unit: determines a respective condition for the IT block instruction using the condition information extracted from the IT instruction and translates the IT block instruction into a microinstruction. The microinstruction includes the respective condition. Execution units conditionally execute the microinstruction based on the respective condition. For each IT block instruction, the instruction translation unit determines a respective state value using the extracted condition information. The state value comprises the lower eight bits of the IT instruction having the lower five bits left-shifted by N-1 bits, where N indicates a position of the IT block instruction in the IT block.
摘要翻译：微处理器包括指令转换单元，其从IT指令中提取条件信息并使IT指令与第一IT块指令融合。对于IT块的每个指令，指令转换单元：使用从IT指令提取的条件信息来确定IT块指令的相应条件，并将IT块指令转换成微指令。微指令包括各自的条件。执行单元根据各自的条件有条件地执行微指令。对于每个IT块指令，指令转换单元使用提取的条件信息确定各自的状态值。状态值包括具有左移N-1位的低5位的IT指令的低8位，其中N表示IT块指令在IT块中的位置。

70. 发明公开

EP2695078A4 MICROPROCESSOR THAT TRANSLATES CONDITIONAL LOAD/STORE INSTRUCTIONS INTO VARIABLE NUMBER OF MICROINSTRUCTIONS 有权转让
标题翻译：微处理器翻译条件电荷/存储说明在可变数量的微指令
公开(公告)号：EP2695078A4
公开(公告)日：2014-07-23
申请号：EP12768614
申请日：2012-04-06
申请人： VIA TECH INC , HENRY G GLENN , COL GERARD M , EDDY COLIN , HOOKER RODNEY E , PARKS TERRY
发明人： HENRY G GLENN , COL GERARD M , EDDY COLIN , HOOKER RODNEY E , PARKS TERRY
IPC分类号： G06F9/30
CPC分类号： G06F9/30043 , G06F9/30072 , G06F9/30076 , G06F9/3017 , G06F9/30174 , G06F9/30189 , G06F9/3859

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