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61. 发明公开

EP2107598A1 SILICON WAFER BEVELING DEVICE, SILICON WAFER MANUFACTURING METHOD, AND ETCHED SILICON WAFER 有权
标题翻译：硅晶片修边装置，硅晶片制造方法及蚀刻硅晶片
公开(公告)号：EP2107598A1
公开(公告)日：2009-10-07
申请号：EP08702776.9
申请日：2008-01-17
申请人： Shin-Etsu Handotai Co., Ltd.
发明人： KATO, Tadahiro
IPC分类号： H01L21/304 , B24B9/00 , H01L21/02
CPC分类号： H01L21/02021 , B24B9/065 , Y10T428/24777
摘要： The invention is directed to a chamfering apparatus for a silicon wafer to chamfer outer edge of a silicon wafer by using a chamfering grindstone, the chamfering apparatus including at least: a holder holding and rotating a silicon wafer; a chamfering grindstone chamfering the outer edge of the silicon wafer held by the holder; and a control apparatus for controlling a chamfered shape by controlling a relative position of the outer edge of the silicon wafer and the chamfering grindstone by numerical control, wherein the control apparatus controls and changes the relative position of the outer edge of the silicon wafer and the chamfering grindstone at the time of chamfering depending on the circumferential position of the silicon wafer held by the holder, a production method, and an etched silicon wafer. This provides a silicon wafer chamfering apparatus, production method and an etched silicon wafer that can suppress variations in the cross-sectional shape dimensions of a chamfered portion after an etching process.
摘要翻译：本发明涉及一种用于硅晶片的倒角装置，该倒角装置通过使用倒角磨石倒角硅晶片的外边缘，所述倒角装置至少包括：保持器，用于保持和旋转硅晶片; 一个斜切磨石，斜切磨削固定在保持器上的硅晶片的外边缘; 以及控制装置，其通过数值控制来控制硅晶片的外缘与倒角磨石的相对位置，从而控制倒角形状，其中，控制装置控制并改变硅晶片的外缘与根据保持器所保持的硅晶片的周向位置进行倒角时的倒角磨石，制造方法以及蚀刻硅晶片。这提供了一种硅晶片倒角装置，制造方法和蚀刻硅晶片，其能够抑制蚀刻工艺之后倒角部分的横截面形状尺寸的变化。

62. 发明公开

EP2051304A1 SEMICONDUCTOR SUBSTRATE, METHOD FOR FORMING ELECTRODE, AND METHOD FOR MANUFACTURING SOLAR CELL 审中-公开
标题翻译：半导体基板，方法形成用于制造太阳能电池的电极和方法
公开(公告)号：EP2051304A1
公开(公告)日：2009-04-22
申请号：EP07790675.8
申请日：2007-07-12
申请人： Shin-Etsu Handotai Co., Ltd. , Shin-Etsu Chemical Co., Ltd.
发明人： ISHIKAWA, Naoki, Isobe R & D Center, Shin-Etsu Handotai Co., Ltd. , OHTSUKA, Hiroyuki, Isobe R & D Center, Shin-Etsu Handotai Co., Ltd. , WATABE, Takenori, Isobe R & D Center, Shin-Etsu Handotai Co., Ltd. , OJIMA, Satoyuki, Isobe R & D Center, Shin-Etsu Handotai Co., Ltd. , UEGURI, Toyohiro, Isobe R & D Center, Shin-Etsu Handotai Co., Ltd.
IPC分类号： H01L31/04 , H01L31/0224 , H01L21/28 , H01L21/288
CPC分类号： H01L31/022425 , C03C8/14 , C03C8/18 , H01L21/2225 , H01L31/05 , H01L2224/48463 , H01L2224/73265 , H01L2924/3025 , Y02E10/50 , H01L2924/00
摘要： The present invention is directed to a semiconductor substrate having at least an electrode formed thereon, in which the electrode has a multilayer structure including two or more layers, of the multilayer structure, at least a first electrode layer directly bonded to the semiconductor substrate contains at least silver and a glass frit, and contains, as an additive, at least one of oxides of Ti, Bi, Zr, V, Nb, Ta, Cr, Mo, W, Mn, Fe, Co, Ni, Si, Al, Ge, Sn, Pb, and Zn, and, of an electrode layer formed on the first electrode layer, at least an uppermost electrode layer to be bonded to a wire contains at least silver and a glass frit and does not contain the additive. This makes it possible to form, on a semiconductor substrate, an electrode adhered to the semiconductor substrate with sufficient adhesive strength and adhered to a wire via solder with sufficient adhesive strength by lowering both contact resistance and interconnect resistance.
摘要翻译：本发明涉及对电极，其至少具有形成在其上的半导体衬底，其中，所述电极具有多层结构的多层结构，包括两层或更多层，至少直接键合到半导体衬底的第一电极层含有在至少银和玻璃料，和包含作为在添加剂，钛，铋，锆，钒，铌，钽，铬，钼，钨，锰，铁，钴，镍，硅，铝的氧化物中的至少一种，锗，锡，铅，和锌，以及，形成在所述第一电极层上的电极层的，至少在最表层的电极层被键合到金属丝至少含有银和玻璃料，而未含有上述添加物。这使得能够形成，在半导体衬底，以电极粘附到足够的粘合强度的半导体衬底，并且通过降低两者的接触电阻和配线电阻经由与足够的粘合强度焊料粘附到导线。

63. 发明公开

EP2034527A1 LIGHT EMITTING ELEMENT AND METHOD FOR FABRICATING THE SAME 审中-公开
标题翻译：赫尔辛基大学教授
公开(公告)号：EP2034527A1
公开(公告)日：2009-03-11
申请号：EP07744286.1
申请日：2007-05-29
申请人： Shin-Etsu Handotai Co., Ltd.
发明人： SUZUKI, Yukari , IKEDA, Jun , ISHIZAKI, Jun-ya , IKEDA, Shunichi
IPC分类号： H01L33/00
CPC分类号： H01L33/0079 , H01L21/02392 , H01L21/02395 , H01L21/02461 , H01L21/02543 , H01L21/02576 , H01L24/05 , H01L33/02 , H01L33/025 , H01L2224/04042 , H01L2224/48463
摘要： A light emitting device comprises a light emitting layer section having a double heterostructure of an n-type cladding layer, an active layer and a p-type cladding layer, each composed of AlGaInP stacked in this order. Supposing a bonding object layer having a first main surface side as p type and a second main surface side as n type, a light extraction side electrode is formed to cover the first main surface partially. An n-type transparent device substrate composed of Group III-V compound semiconductor having greater band gap energy than the active layer is bonded to the second main surface of the bonding object layer. On one sides of the transparent device substrate and the bonding object layer, a bonding surface to the other is formed, and an InGaP intermediate layer is formed to have a high concentration Si doping layer formed on the bonding surface side.
摘要翻译：发光器件包括具有由依次堆叠的AlGaInP构成的n型包覆层，有源层和p型覆层的双异质结构的发光层部。假设具有第一主表面侧为p型，第二主面侧为n型的接合对象层，形成有一部分覆盖第一主面的光提取侧电极。由具有比有源层更大的带隙能量的III-V族化合物半导体构成的n型透明器件基板被接合到接合目标层的第二主表面。在透明器件基板和接合目标层的一侧上，形成彼此的接合表面，并且形成InGaP中间层以在接合表面侧上形成高浓度的Si掺杂层。

64. 发明公开

EP2023375A1 BONDED WAFER MANUFACTURING METHOD 审中-公开
标题翻译：结合晶圆制造方法
公开(公告)号：EP2023375A1
公开(公告)日：2009-02-11
申请号：EP07743299.5
申请日：2007-05-14
申请人： Shin-Etsu Handotai Co., Ltd.
发明人： SOETA, Yasutsugu , NOTO, Nobuhiko
IPC分类号： H01L21/02 , H01L21/3065 , H01L21/762 , H01L27/12
CPC分类号： H01L21/76254 , H01L21/3065
摘要： The present invention provides a method for manufacturing a bonded wafer by an ion implantation delamination method, the method including at least the steps of bonding a base wafer with a bond wafer having a microbubble layer formed by ion implantation, delaminating the wafers along the micro bubble layer as a boundary, and removing a periphery of a thin film formed on the base wafer by the delamination step, wherein at least the thin-film periphery removal step after the delamination step is performed by dry etching that supplies an etching gas from a nozzle, and the dry etching is performed by adjusting an inner diameter of the gas-jetting port of the nozzle, and a distance between the gas-jetting port of the nozzle and a surface of the thin film. As a result of this, there is provided the method for manufacturing the bonded wafer, in which removal of the thin-film periphery can be easily performed and a removal width is also reproducibly obtained well in the thin-film periphery removal step, and degradation in quality of the thin film can be effectively prevented.
摘要翻译：本发明提供一种通过离子注入剥离方法制造键合晶片的方法，该方法至少包括以下步骤：将基底晶片与具有通过离子注入形成的微泡层的键合晶片键合，沿着微泡使层叠层剥离通过剥离工序除去在基底基板上形成的薄膜的周边，其特征在于，至少剥离工序后的薄膜周边除去工序通过从喷嘴供给蚀刻气体的干式蚀刻来进行并且通过调节喷嘴的喷气口的内径以及喷嘴的喷气口与薄膜的表面之间的距离来执行干法蚀刻。结果，提供了一种制造键合晶片的方法，其中能够容易地执行除去薄膜周边，并且在薄膜周边除去步骤中也可重现地获得除去宽度，并且降解可以有效地防止薄膜的质量。

65. 发明授权

EP1087041B1 PRODUCTION METHOD FOR SILICON WAFER AND SILICON WAFER 有权
标题翻译：工艺硅片和硅晶片
公开(公告)号：EP1087041B1
公开(公告)日：2009-01-07
申请号：EP00905367.9
申请日：2000-02-25
申请人： Shin-Etsu Handotai Co., Ltd.
发明人： ABE, Takao Isobe R & D Center , AIHARA, Ken Isobe R & D Center , AKIYAMA, Shoji Isobe R & D Center , IGARASHI, Tetsuya Takefu Plant , QU, Weifeng Isobe R & D Center , HAYAMIZU, Yoshinori Isobe R & D Center , SAITO, Shigeru Isobe R & D Center
IPC分类号： C30B29/06 , H01L21/322 , H01L27/12
CPC分类号： C30B29/06 , C30B15/00 , H01L21/3225 , Y10T428/21
摘要： A silicon wafer production method comprising the steps of growing, by a Czochralski method, a silicon single crystal bar having a resistivity of at least 100 OMEGA .cm and an initial interstitial oxygen concentration of 10 to 25 ppma, processing the silicon single crystal bar into a wafer, and oxygen-precipitation-heat-treating the wafer to reduce a residual interstitial oxygen concentration in the wafer to up to 8 ppma. A silicon wafer produced as above is small in resistivity reduction when heat-treated during a device production or the like. A silicon wafer produced and heat-treated to have the above initial interstitial oxygen concentration and residual interstitial oxygen concentration independently of resistivity can eliminate slip dislocation in the subsequent heat treating. An epitaxial layer formed on the surface of the silicon wafer can form a high-resistivity epitaxial wafer free from slip dislocation and applicable to various devices.

66. 发明授权

EP1052313B1 SILICON WAFER AND METHOD OF MANUFACTURE THEREOF 有权
标题翻译：硅片上，方法及其
公开(公告)号：EP1052313B1
公开(公告)日：2008-10-08
申请号：EP99973311.6
申请日：1999-12-01
申请人： Shin-Etsu Handotai Co., Ltd.
发明人： KOBAYASHI, Norihiro, Isobe R & D Center, , AKIYAMA, Shoji, Isobe R & D Center, , ABE, Takao, Isobe R & D Center,
IPC分类号： C30B29/06 , C30B33/12 , H01L21/306 , C30B33/00
CPC分类号： H01L21/02008 , C30B29/06 , C30B33/00 , H01L21/322
摘要： A method of manufacturing a silicon wafer comprises a plurality of steps of polishing at least one side of a wafer, in which the last of the steps includes a heat treatment in a hydrogen-argon atmosphere using a device for heating and cooling suddenly. The method provides wafers with smooth surface free from distortion, scratches and slip dislocations, and productivity also increases.

67. 发明公开

EP1975283A1 PROCESS FOR PRODUCING SILICON SINGLE CRYSTAL WAFER 有权
标题翻译： VERFAHREN ZUR HERSTELLUNG EINES SILICIUMEINKRISTALLWAFERS
公开(公告)号：EP1975283A1
公开(公告)日：2008-10-01
申请号：EP06842997.6
申请日：2006-12-21
申请人： Shin-Etsu Handotai Co., Ltd.
发明人： EBARA, Koji
IPC分类号： C30B29/06 , C30B33/02 , H01L21/322
CPC分类号： H01L21/3225 , C30B15/04 , C30B15/203 , C30B29/06 , C30B33/02
摘要： The present invention provides a method for manufacturing a silicon single crystal wafer in which a silicon single crystal ingot is pulled by a CZ method, and a wafer sliced from the ingot is subjected to a rapid thermal annealing, wherein wafers sliced from the ingot which has been pulled while changing a pulling rate are subjected to rapid thermal annealings in various heat treatment temperatures, oxide dielectric breakdown voltage measurements are performed to get a relation between the pulling rate and the heat treatment temperatures, and a result of the oxide dielectric breakdown voltage measurements in advance, conditions of a pulling rate and a heat treatment temperature are determined based on the relation so that the whole area thereof in the radial direction may become N region after the rapid thermal annealing, and the pulling of the ingot and the rapid thermal annealing are performed to thereby manufacture the silicon single crystal wafer. As a result of this, a manufacturing method capable of efficiently and certainly manufacturing the silicon wafer in which a DZ layer can be secured in a wafer surface layer and an oxide precipitate can be formed in a bulk region of the wafer is provided.
摘要翻译：本发明提供了一种通过CZ法拉制硅单晶锭的硅单晶晶片的制造方法，并且对从该锭切片的晶片进行快速热退火，其中从具有在改变拉伸速率的同时被拉伸的各种热处理温度下进行快速热退火，进行氧化物绝缘击穿电压测量以获得牵引速率和热处理温度之间的关系，以及氧化物绝缘击穿电压测量的结果根据关系，预先设定拉伸速度和热处理温度的条件，使得其在径向方向上的整个面积可以在快速热退火后成为N区域，并且锭子的拉动和快速热退火从而制造硅单晶晶片。作为其结果，可以在晶片的主体区域中形成能够有效且可靠地制造可在晶片表面层中确保DZ层的硅晶片和氧化物沉淀物的制造方法。

68. 发明授权

EP1074643B1 SINGLE-CRYSTAL SILICON WAFER HAVING FEW CRYSTAL DEFECTS AND METHOD FOR MANUFACTURING THE SAME 有权
标题翻译：随着对结晶缺陷少和方法的单晶ITS
公开(公告)号：EP1074643B1
公开(公告)日：2008-08-20
申请号：EP99972699.5
申请日：1999-11-11
申请人： Shin-Etsu Handotai Co., Ltd.
发明人： IIDA, Makoto, Isobe R & D Center , KIMURA, Masanori, Isobe R & D Center , MURAOKA, Shozo, Isobe R & D Center
IPC分类号： C30B29/06
CPC分类号： C30B29/06 , C30B15/14 , C30B15/203 , C30B15/206
摘要： A single-crystal silicon manufacturing method for growing a silicon single crystal by a Czochralski method. A crystal is pulled up at a speed within a region enclosed by the boundary line between the V-rich region and the N-region and the boundary line between the N-region and the I-rich region shown, in the defect distribution diagram whose abscissa is the distance D [mm] from the center to the periphery of the crystal and whose ordinate is the value of F/G [mm / DEG C.min] where F [mm/min] is the pull rate, and G [ DEG C/mm] is the average of the temperature gradient in the crystal along the pull axis in the temperature range of the melting point of silicon to 1,400 DEG C. It takes 700 minutes or less to pass through the temperature zone from 900 DEG C to 600 DEG C in the crystal. All the surface of the single-crystal silicon wafer grown by the Czochralski method is an N-region in which OSF is produced not by a single-step thermal oxidation but by a two-step thermal oxidation.

69. 发明公开

EP1953808A1 METHOD FOR PRODUCING EPITAXIAL WAFER AND EPITAXIAL WAFER 审中-公开
标题翻译： VERFAHREN ZUR HERSTELLUNG EINES外星人外套
公开(公告)号：EP1953808A1
公开(公告)日：2008-08-06
申请号：EP06822227.2
申请日：2006-10-25
申请人： Shin-Etsu Handotai Co., Ltd.
发明人： KANAYA, Koichi , OHNISHI, Masato
IPC分类号： H01L21/205 , C23C16/24 , H01L21/02
CPC分类号： C30B25/16 , C30B25/02 , C30B25/165 , C30B29/06 , H01L21/02381 , H01L21/02532 , H01L21/0262 , H01L21/02634
摘要： The present invention provides a method for manufacturing an epitaxial wafer by supplying a raw material gas onto a silicon wafer to perform vapor-phase growth of an epitaxial layer, wherein a thickness of the epitaxial layer that is formed at a peripheral portion of the silicon wafer is controlled by controlling a growth rate and/or a growth temperature of the epitaxial layer that is subjected to vapor-phase growth. As a result, there is provided the method that enables manufacturing an epitaxial wafer having a small roll-off value by controlling a thickness of an epitaxial layer near the outermost periphery at the time of epitaxial growth.
摘要翻译：本发明提供一种通过将原料气体供给到硅晶片上以进行外延层的气相生长来制造外延晶片的方法，其中形成在硅晶片的周边部分的外延层的厚度通过控制经历气相生长的外延层的生长速率和/或生长温度来控制。结果，提供了通过在外延生长时控制最外周附近的外延层的厚度，能够制造具有小滚降值的外延晶片的方法。

70. 发明公开

EP1876651A1 SOLAR CELL MANUFACTURING METHOD, SOLAR CELL, AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD 有权转让
标题翻译：太阳能电池制造方法，太阳能电池及其制造方法半导体元件
公开(公告)号：EP1876651A1
公开(公告)日：2008-01-09
申请号：EP06731542.4
申请日：2006-04-11
申请人： Shin-Etsu Handotai Co., Ltd , Naoetsu Electronics Co., Ltd. , Shin-Etsu Chemical Company, Ltd.
发明人： OHTSUKA, Hiroyuki c/o Isobe R & D Center , TAKAHASHI, Masatoshi c/o Isobe R & D Center , ISHIKAWA, Naoki c/o Isobe R & D Center , SAISU, Shigenori c/o Isobe R & D Center , UEGURI, Toyohiro c/o Isobe R & D Center , OJIMA, Satoyuki c/o Isobe R & D Center , WATABE, Takenori c/o Isobe R & D Center , AKATSUKA, Takeshi Naoetsu Electronics Co., Ltd. , ONISHI, Tsutomu c/o Naoetsu Electronics Co., Ltd.
IPC分类号： H01L31/04
摘要： The present invention is a method for manufacturing a solar cell by forming a p-n junction in a semiconductor substrate having a first conductivity type, wherein, at least: a first coating material containing a dopant and an agent for preventing a dopant from scattering, and a second coating material containing a dopant, are coated on the semiconductor substrate having the first conductivity type so that the second coating material may be brought into contact with at least the first coating material; and, a first diffusion layer formed by coating the first coating material, and a second diffusion layer formed by coating the second coating material the second diffusion layer having a conductivity is lower than that of the first diffusion layer are simultaneously formed by a diffusion heat treatment; a solar cell manufactured by the method; and a method for manufacturing a semiconductor device. It is therefore possible to provide the method for manufacturing the solar cell, which can manufacture the solar cell whose photoelectric conversion efficiency is improved at low cost and with a simple and easy method by suppressing surface recombination in a portion other than an electrode of a light-receiving surface and recombination within an emitter while obtaining ohmic contact; the solar cell manufactured by the method; and the method for manufacturing the semiconductor device.
摘要翻译：本发明是一种用于通过形成具有在半导体衬底形成pn结的制造太阳能电池的方法的第一导电型，worin，至少包括：一第一涂层材料含有掺杂剂以及用于从飞散防止掺杂剂的药剂，和一个含有掺杂剂的第二涂层材料，被涂覆在具有第一导电类型，以便做了第二涂层材料可被带入与至少第一涂层材料接触的半导体衬底; 并且，通过涂布在第一涂层材料形成的第一扩散层，和通过涂布该第二涂覆材料具有导电性的第二扩散层所形成的第二扩散层是低于所述第一扩散层的同时通过扩散热处理而形成 ; 通过该方法制造的太阳能电池; 和用于制造半导体器件的方法。因此，可以提供该方法用于制造太阳能电池，其可制造太阳能电池谁的光电转换效率通过在比在光的电极以外的部分抑制表面复合以低成本和利用简单和容易的方法是提高 - 接收表面和复合内发射极的同时，获得欧姆接触; 通过该方法制造的太阳能电池; 和用于半导体装置的制造方法。

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