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61. 发明公开

EP2284838A1 Semiconductor memory, memory controller, system, and operating method of semiconductor memory 有权
标题翻译： Halbleiterspeicher，Speichersteuerung，System und Betriebsverfahrenfüreinen Halbleiterspeicher
公开(公告)号：EP2284838A1
公开(公告)日：2011-02-16
申请号：EP10182639.4
申请日：2008-02-27
申请人： Fujitsu Semiconductor Limited
发明人： Kawabata, Kuninori
IPC分类号： G11C11/406
CPC分类号： G11C11/406 , G11C11/40603 , G11C11/40615
摘要： A memory controller controlling operations of a plurality of semiconductor memories each having dynamic memory cells, in response to an access request from a system controller and a refresh request, the memory controller comprising: a refresh request generation circuit (14) periodically outputting the refresh request; a main refresh address counter (MRAC) changing a main block address held in the main refresh address counter, when the main block address coincides with an access block address corresponding to the access request, and sequentially generating a main row address and the main block address in synchronization with a main count signal; a sub refresh address counter (SRAC) set valid when the main block address coincides with the access block address, receiving, as a sub block address and a sub row address, the main block address and the main row address transferred from the main refresh address counter, sequentially generating the sub row address in synchronization with a sub count signal, and set invalid after outputting a final sub row address; an address selection circuit (RASEL, BASEL) selecting addresses not coinciding with the access block address, out of the main block address and the main row address, and the sub block address and the sub row address, and outputting the selected addresses; a counter control circuit (CCNT) outputting, in response to a refresh request, one of the main count signal and the sub count signal corresponding to the addresses output by the address selection circuit; a refresh counter control circuit (MCMP, SW1, F/F, AND1, SW2, SCMP, AND2) controlling operations of the main refresh address counter, the sub refresh address counter, the address selection circuit, and the counter control circuit, and making the sub refresh address counter operate with priority over the main refresh address counter during a period in which the sub refresh address counter is valid; and an operation control circuit (16) outputting an access control signal in response to the access request, and outputting a refresh control signal in response to the refresh.
摘要翻译：存储器控制器，响应于来自系统控制器的访问请求和刷新请求，控制各自具有动态存储单元的多个半导体存储器的操作，所述存储器控制器包括：周期性地输出刷新请求的刷新请求生成电路（14） ; 当主块地址与对应于访问请求的访问块地址一致时，主要刷新地址计数器（MRAC）改变保存在主刷新地址计数器中的主块地址，并且顺序地产生主行地址和主块地址与主计数信号同步; 当主块地址与访问块地址一致时，子刷新地址计数器（SRAC）设置为有效，接收从主刷新地址传送的主块地址和主行地址作为子块地址和子行地址计数器，与子计数信号同步顺序地产生子行地址，并在输出最后的子行地址后设置为无效; 选择地址选择电路（RASEL，BASEL），从主块地址和主行地址以及子块地址和子行地址中选择与访问块地址不一致的地址，并输出所选择的地址; 响应于刷新请求，计数器控制电路（CCNT）输出与地址选择电路输出的地址对应的主计数信号和副计数信号之一; 控制主刷新地址计数器，副刷新地址计数器，地址选择电路和计数器控制电路的操作的刷新计数器控制电路（MCMP，SW1，F / F，AND1，SW2，SCMP，AND2）子刷新地址计数器在副刷新地址计数器有效的时间段内优先地操作主刷新地址计数器; 以及响应于所述访问请求输出访问控制信号的操作控制电路（16），并且响应于所述刷新而输出刷新控制信号。

62. 发明公开

EP2284739A2 Design support program, design support device, and design support method 审中-公开
标题翻译：设计支持程序，设计支持设备和设计支持方法
公开(公告)号：EP2284739A2
公开(公告)日：2011-02-16
申请号：EP10167467.9
申请日：2010-06-28
申请人： Fujitsu Semiconductor Limited
发明人： Ushiyama, Kenichi
IPC分类号： G06F17/50
CPC分类号： G06F17/5077
摘要： A design support program executed by a computer includes computer readable program code for causing the computer to execute operations of: selecting a first hierarchy (e.g. "6") which has first characteristic information included in wiring layer structure information in a storage device (100), the first characteristic information differing from characteristic information of other hierarchies ("1" to "5") included in the wiring layer structure information; generating second characteristic information including the first characteristic information; copying wiring layer structure information; and converting the first characteristic information included in the copied wiring layer structure information into the second characteristic information to obtain converted wiring layer structure information (101).
摘要翻译：由计算机执行的设计支持程序包括用于使计算机执行以下操作的计算机可读程序代码：选择具有包括在存储设备（100）中的布线层结构信息中的第一特性信息的第一层（例如“6”），，第一特征信息不同于包括在布线层结构信息中的其他分层结构（“1”到“5”）的特征信息; 生成包括第一特征信息的第二特征信息; 复制布线层结构信息; 以及将包含在复制的布线层结构信息中的第一特性信息转换成第二特性信息，以获得转换的布线层结构信息（101）。

63. 发明授权

EP1976014B1 CMOS imaging device 有权
标题翻译： CMOS摄像装置
公开(公告)号：EP1976014B1
公开(公告)日：2011-01-05
申请号：EP08158577.0
申请日：2004-07-20
申请人： Fujitsu Semiconductor Limited
发明人： Ohkawa, Narumi, FUJITSU LIMITED
IPC分类号： H01L27/146 , H04N5/335
CPC分类号： H01L27/14609 , H01L27/14603 , H01L27/1463 , H01L27/14641 , H01L27/14689 , H04N5/37457

64. 发明公开

EP2267758A2 Method for manufacturing a ferroelectric memory 有权
标题翻译： Herstellungsverfahrenfüreinen ferroelekrischen Speicher
公开(公告)号：EP2267758A2
公开(公告)日：2010-12-29
申请号：EP10179525.0
申请日：2005-06-02
申请人： Fujitsu Semiconductor Limited
发明人： Wang, Wensheng
IPC分类号： H01L21/02 , H01L21/768 , H01L21/3205 , H01L27/115
CPC分类号： H01L21/76832 , H01L21/76802 , H01L21/76814 , H01L21/76826 , H01L21/76829 , H01L24/05 , H01L27/11502 , H01L27/11507 , H01L28/57 , H01L28/75 , H01L2224/02126 , H01L2224/02166 , H01L2224/05624 , H01L2924/13091 , H01L2924/14 , H01L2924/19041 , H01L2924/30105 , H01L2924/01029 , H01L2924/00
摘要： Ferroelectric capacitors (42) are formed over a semiconductor substrate (10), then, a barrier film (46) directly covering the ferroelectric capacitors (42) is formed. Thereafter, wirings (56a etc.) connected to the ferroelectric capacitors (42) are formed. Further, a barrier film (58) is formed at a position higher than the wirings (56a etc.). In forming the barrier film (46), a film stack is formed, the film stack including at least two kinds of diffusion preventive films (46a and 46b) having different components and preventing diffusion of hydrogen or water.
摘要翻译：铁电电容器（42）形成在半导体衬底（10）上，然后形成直接覆盖铁电电容器（42）的阻挡膜（46）。之后，形成与强电介质电容器（42）连接的配线（56a等）。此外，在高于布线（56a等）的位置处形成阻挡膜（58）。在形成阻挡膜（46）时，形成膜堆叠，所述膜堆叠包括至少两种具有不同成分的防扩散膜（46a和46b），并防止氢或水的扩散。

66. 发明公开

EP2249387A1 Imaging device 有权
公开(公告)号：EP2249387A1
公开(公告)日：2010-11-10
申请号：EP10169185.5
申请日：2005-03-28
申请人： Fujitsu Semiconductor Limited
发明人： Inoue, Tadao , Yamamoto, Katsuyoshi , Kobayashi, Hiroshi
IPC分类号： H01L27/146 , H04N5/335
CPC分类号： H01L27/14603 , H01L27/14609 , H01L27/14621 , H01L27/14627 , H01L27/1463 , H01L27/14643 , H01L27/14645 , H01L31/03529 , H04N5/361 , Y02E10/50
摘要： A first diffusion region (N1) constituting a photodiode in each pixel stores carriers generated according to incident light. A second diffusion region (P+) is formed at a surface of the first diffusion region to cover a peripheral part of the first diffusion region. In the peripheral part of the first diffusion region, crystal defects tend to occur by a process of forming an isolation region (STI) and a process of forming a gate electrode (TG), so that dark current noise tends to occur. The second diffusion region functions as a protection layer which prevents occurrence of crystal defects in a manufacturing process. The second diffusion region is not formed on a central part of the surface of the first diffusion region where crystal defects do not tend to occur. In the first diffusion region where the second diffusion region is not formed, the thickness of a depletion layer can be increased, which can improve light detection sensitivity. This can improve detection sensitivity of the photodiode without increasing the dark current noise.

67. 发明公开

EP2246859A1 Semiconductor memory device, and method of controlling the same 有权
标题翻译： Halbleiterspeicher und Steuerverfahrendafür
公开(公告)号：EP2246859A1
公开(公告)日：2010-11-03
申请号：EP10165897.9
申请日：2000-09-27
申请人： Fujitsu Semiconductor Limited
发明人： Fujioka, Shinya , Kawakubo, Tomohiro , Nishimura, Koichi , Sato, Kotoku
IPC分类号： G11C11/406 , G11C5/14
CPC分类号： G11C5/14 , G11C5/147 , G11C11/406 , G11C2207/2227
摘要： A semiconductor memory device comprises an internal voltage generator (18) which, when activated, generates an internal voltage to be supplied to an internal circuit. Operating the internal voltage generator (18) consumes a predetermined amount of the power. In response to a control signal from the exterior, an entry circuit (14) inactivates the internal voltage generator (18). When the internal voltage generator (18) is inactivated, the internal voltage is not generated, thereby reducing the power consumption. By the control signal from the exterior, therefore, a chip can easily enter a low power consumption mode. The internal voltage generator (18) is exemplified by a booster (28) for generating the boost voltage of a word line connected with memory cells, a substrate voltage generator (34) for generating a substrate voltage, or a precharging voltage generator (30) for generating the precharging voltage of bit lines to be connected with the memory cells. During the low power consumption mode, an external voltage supplying circuit supplies a power supply voltage supplied from the exterior as the internal voltage to a predetermined internal circuit. Even when the internal voltage generator (18) is inactivated, therefore, the power supply voltage is supplied to the power supply terminal of each internal circuit, which results in preventing a leak path.
摘要翻译：半导体存储器件包括内部电压发生器（18），其在被激活时产生将被提供给内部电路的内部电压。操作内部电压发生器（18）消耗预定量的功率。响应于来自外部的控制信号，入口电路（14）使内部电压发生器（18）失活。当内部电压发生器（18）失活时，不产生内部电压，从而降低功耗。因此，通过来自外部的控制信号，芯片可以容易地进入低功耗模式。内部电压发生器（18）例如是用于产生与存储单元连接的字线的升压电压的升压器（28），用于产生衬底电压的衬底电压发生器（34）或预充电电压发生器（30）用于产生要与存储器单元连接的位线的预充电电压。在低功耗模式期间，外部电压供给电路将从外部供给的电源电压作为内部电压供给到规定的内部电路。因此，即使当内部电压发生器（18）失活时，电源电压被提供给每个内部电路的电源端子，这导致防止泄漏路径。

68. 发明公开

EP2242095A1 SEMICONDUCTOR DEVICE AND ITS MANUFACTURING METHOD 有权转让
标题翻译：半导体器件及其制造方法
公开(公告)号：EP2242095A1
公开(公告)日：2010-10-20
申请号：EP07860452.7
申请日：2007-12-28
申请人： Fujitsu Semiconductor Limited
发明人： OSAJIMA, Toru
IPC分类号： H01L21/822 , H01L21/60 , H01L21/66 , H01L27/04
CPC分类号： H01L24/06 , H01L22/32 , H01L23/5286 , H01L24/05 , H01L24/45 , H01L24/48 , H01L24/49 , H01L27/0203 , H01L2224/02166 , H01L2224/04042 , H01L2224/05553 , H01L2224/05554 , H01L2224/05556 , H01L2224/05624 , H01L2224/06153 , H01L2224/45144 , H01L2224/48091 , H01L2224/48247 , H01L2224/48465 , H01L2224/48624 , H01L2224/49175 , H01L2224/49431 , H01L2924/00014 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01022 , H01L2924/01023 , H01L2924/01029 , H01L2924/01033 , H01L2924/0105 , H01L2924/01074 , H01L2924/01076 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/10253 , H01L2924/1305 , H01L2924/1306 , H01L2924/13091 , H01L2924/14 , H01L2924/181 , H01L2924/19041 , H01L2924/30107 , H01L2924/00
摘要： A first external connection terminal (14) at a first row (2) is disposed to position at upside of a first I/O cell (12), and a second external connection terminal (15) at a second row (3) is formed at upside of a boundary portion between two adjacent first I/O cells (12). Here, the first external connection terminal (14) and the second external connection terminal (15) are disposed to be separated for a predetermined distance so as not to have an overlapped portion with each other, and formed in an identical layer. According to the constitution, it is possible to prevent disadvantages such as characteristic deterioration of a semiconductor integrated circuit and accuracy deterioration of an electrical inspection while fully securing an electrical connection of probe needles with the first external connection terminal (14) and the second external connection terminal (15) at the electrical inspection time, and enabling higher integration and higher function of a semiconductor chip (1) by shortening a distance between the adjacent first external connection terminal (14) and second external connection terminal (15) at the first row (2) and the second row (3) as much as possible.
摘要翻译：第一行（2）处的第一外部连接端子（14）被布置成位于第一I / O单元（12）的上侧，并且第二行（3）处的第二外部连接端子（15）被形成在两个相邻的第一I / O单元（12）之间的边界部分的上方。这里，第一外部连接端子（14）和第二外部连接端子（15）被设置为分离预定的距离，从而不具有彼此重叠的部分，并形成为相同的层。根据该结构，能够在充分确保探针针与第一外部连接端子（14）和第二外部连接端子（14）的电连接的同时，防止诸如半导体集成电路的特性劣化和电气检查的精确度劣化通过缩短在第一行处的相邻的第一外部连接端子（14）和第二外部连接端子（15）之间的距离来实现半导体芯片（1）的更高的集成度和更高的功能（2）和第二行（3）尽可能多。

69. 发明授权

EP1659591B1 Semiconductor memory 有权
公开(公告)号：EP1659591B1
公开(公告)日：2010-09-22
申请号：EP06002915.4
申请日：2003-08-01
申请人： Fujitsu Semiconductor Limited
发明人： Koga, Toru, c/o Fujitsu Limited
IPC分类号： G11C7/10 , G11C11/4096
CPC分类号： G11C7/1006 , G11C11/4096 , G11C11/4097 , G11C29/848 , G11C2207/002 , H01L27/0207 , H01L27/10885

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