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51. 发明公开

EP4086952A1 SEMICONDUCTOR DEVICE PACKAGING LEADFRAME ASSEMBLY AND METHOD THEREFOR 无效
公开(公告)号：EP4086952A1
公开(公告)日：2022-11-09
申请号：EP22169151.2
申请日：2022-04-21
申请人： NXP B.V.
发明人： Chang, Yeou Chian , Huang, Chao Hui
IPC分类号： H01L23/433 , H01L23/495
摘要： A method of manufacturing a semiconductor device is provided. The method includes forming a package leadframe assembly. The package leadframe includes a plurality of leads. An adhesive is placed on a portion of the plurality of leads. A die pad is placed onto the adhesive. A portion of the die pad overlaps the portion of the plurality of leads. A semiconductor die is attached to the die pad. A molding compound encapsulates the semiconductor die and a portion of the package leadframe assembly.

52. 发明公开

EP4062446A1 POWER MODULE PACKAGE AND PACKAGING TECHNIQUES 审中-实审
公开(公告)号：EP4062446A1
公开(公告)日：2022-09-28
申请号：EP20845268.0
申请日：2020-12-18
申请人： Allegro MicroSystems, LLC
发明人： LIU, Shixi, Louis , HEALEY, Natasha , NIKAM, Rishikesh
IPC分类号： H01L23/36 , H01L23/495

53. 发明公开

EP4057338A1 METAL SUBSTRATE STRUCTURE AND METHOD OF MANUFACTURING A METAL SUBSTRATE STRUCTURE FOR A SEMICONDUCTOR POWER MODULE AND SEMICONDUCTOR POWER MODULE 审中-实审转让
公开(公告)号：EP4057338A1
公开(公告)日：2022-09-14
申请号：EP21161694.1
申请日：2021-03-10
申请人： Hitachi Energy Switzerland AG
发明人： Guillon, David , Beyer, Harald , Ehrbar, Roman
IPC分类号： H01L23/373 , H01L23/495 , H01L23/498
摘要： A metal substrate structure (10) for a semiconductor power module comprises a metal top layer (11) having at least one recess which is limited by an edge (14) of the metal top layer (11), wherein the metal top layer (11) further comprises at least one stress relief structure in an area adjacent to the edge (14). The metal substrate structure (10) further comprises a metal bottom layer (13) and a dielectric layer (12) which is coupled with both the metal top layer (11) and the metal bottom layer (13) and formed in between with respect to a stacking direction (A).

54. 发明公开

EP4040481A1 ELECTRONIC DEVICE 审中-公开
公开(公告)号：EP4040481A1
公开(公告)日：2022-08-10
申请号：EP22153616.2
申请日：2022-01-27
申请人： InnoLux Corporation
发明人： CHI, Jen-Hai , YEH, Chen-Lin , HSIEH, Chih-Yung
IPC分类号： H01L23/498 , H01L23/495 , H01L23/538 , H01L25/16
摘要： The disclosure provides an electronic device, including a substrate, a first conductor layer, a first insulating layer, an electronic component, and a driving structure. The first conductor layer is arranged on the substrate. The first insulating layer is disposed on the first conductor layer. The electronic component is arranged on the first insulating layer and coupled to the first conductor layer. The driving structure is coupled to the electronic component. The electronic device in the disclosure can have improved structural reliability.

55. 发明授权

EP3703121B1 SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE 有权
公开(公告)号：EP3703121B1
公开(公告)日：2022-08-10
申请号：EP17930124.7
申请日：2017-10-26
发明人： UMEDA Soichiro , KYUTOKU Atsushi
IPC分类号： H01L23/48 , H01L23/495 , H01L23/498 , H01L23/00

56. 发明公开

EP4035205A1 MOLDED INTERCONNECTS IN BRIDGES FOR INTEGRATED-CIRCUIT PACKAGES 审中-实审
公开(公告)号：EP4035205A1
公开(公告)日：2022-08-03
申请号：EP20869146.9
申请日：2020-06-26
申请人： Intel Corporation
发明人： ONG, Jenny Shio Yin , LIM, Seok Ling , CHEAH, Bok Eng , KONG, Jackson Chung Peng
IPC分类号： H01L23/495 , H01L23/498 , H01L23/58

57. 发明公开

EP4016621A1 POWER AMPLIFIER DEVICE 审中-公开
公开(公告)号：EP4016621A1
公开(公告)日：2022-06-22
申请号：EP21215192.2
申请日：2021-12-16
申请人： Ampleon Netherlands B.V.
发明人： Van der Zanden, Josephus Henricus Bartholomeus
IPC分类号： H01L23/66 , H01L23/00 , H03F3/19 , H01L23/495
摘要： The present invention relates to a power amplifier device. The present invention further relates to a semiconductor die used or to be used in such a power amplifier device. The present invention particularly relates to power amplifier devices operable at radiofrequency, RF, frequencies, more in particular in a frequency range between 100 MHz and 40 GHz.
The power amplifier device of the present invention comprises a semiconductor die on which a power transistor is integrated. The semiconductor die comprises a shunt network comprising a plurality of first bondwires arranged in series with a first capacitor, which first capacitor is arranged near an input side of the power transistor. The shunt network is configured for tuning out the output capacitance of the power transistor.
According to the transistor, the power amplifier device comprises a pair of coupled lines formed on the semiconductor die, wherein a first line of the pair of coupled lines is connected in series with the input of the power transistor, and wherein a second line of the pair of coupled lines is incorporated in the shunt network in series with the first plurality of bondwires and the first capacitor.

58. 发明公开

EP4016614A1 METHOD OF MANUFACTURING MULTI-DIE SEMICONDUCTOR DEVICES 有权
公开(公告)号：EP4016614A1
公开(公告)日：2022-06-22
申请号：EP21214666.6
申请日：2021-12-15
申请人： STMicroelectronics S.r.l.
发明人： CREMA, Paolo
IPC分类号： H01L23/495 , H01L21/48
摘要： In a method of manufacturing a multi-die semiconductor device (10), a metal leadframe is provided which includes a die pad (100) and electrically-conductive leads (102) arranged around the die pad. A first (12) and a second (14) semiconductor dice are arranged onto the die pad. A laser-activatable material is provided onto the dice (12, 14) and the leads (102), and a set of laser-activated lines is patterned which includes a first subset of lines coupling selected bonding pads of the dice (12, 14) to selected leads (102), a second subset of lines coupling selected bonding pads of the dice (12, 14) amongst themselves, and a third subset of lines coupling the lines in the second subset of lines to at least one line in the first subset of lines, and/or to at least one electrically-conductive lead. A first metallic layer is deposited onto the laser-activated lines to provide respective first, second and third subsets of electrically-conductive lines. A second metallic layer is selectively deposited onto the first and second subsets of electrically-conductive lines by means of electroplating to provide respective first (16C', 16C) and second (16B', 16B) subsets of electrically-conductive tracks. The electrically-conductive lines in said third subset of electrically-conductive lines are selectively removed.

59. 发明公开

EP4016590A1 METHOD OF MANUFACTURING SEMICONDUCTOR DEVICES AND CORRESPONDING SEMICONDUCTOR DEVICE 审中-公开
公开(公告)号：EP4016590A1
公开(公告)日：2022-06-22
申请号：EP21215260.7
申请日：2021-12-16
申请人： STMicroelectronics S.r.l.
发明人： FONTANA, Fulvio Vittorio , DERAI, Michele
IPC分类号： H01L21/48 , H01L23/495
摘要： A method of manufacturing semiconductor devices such as QFN-mr packages, for instance, comprises arranging (1001) one or more semiconductor chips or dice (2000) at a first surface of a leadframe (1000) and forming (1005) an insulating encapsulation onto the leadframe (1000) having the semiconductor chip(s) arranged thereon at the first surface of the leadframe. Etching (1006) is applied at a second surface of the leadframe (1000) opposed to the first surface in order provide electrical contacts having a distal (bottom) surface as well as well as flanks left uncovered by the insulating encapsulation. Etching at the second surface of the leadframe (1000) is via an etching mask (3000) covering the electrical contacts as well as at least one connecting bar electrically coupling a plurality of electrical contacts. The etching mask is removed (3001) and the electrical contacts (12) and the connecting bar(s) thus exposed are used as electroplating electrodes in (e.g., tin) electroplating (3002) of the distal surface and the flanks of the electrical contacts (12) with the connecting bar(s) finally removed (1009, 1009A) during device singulation, for instance.

60. 发明公开

EP4004978A1 ELEKTRISCHES UND/ODER ELEKTRONISCHES BAUELEMENT UND KONTAKTANORDNUNG 有权
公开(公告)号：EP4004978A1
公开(公告)日：2022-06-01
申请号：EP20750192.5
申请日：2020-07-23
申请人： Robert Bosch GmbH
发明人： HEMMERT, Reiner , SUENNER, Thomas , SCHIELE, Christian
IPC分类号： H01L23/495 , H05K3/32

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