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51. 发明授权

EP1906313B1 Memory management in a shared memory system 有权转让
公开(公告)号：EP1906313B1
公开(公告)日：2018-11-07
申请号：EP07004381.5
申请日：2007-03-02
申请人： Avago Technologies General IP (Singapore) Pte. Ltd.
发明人： Pong, Fong
IPC分类号： G06F12/08 , G06F12/0813 , G06F12/0817
CPC分类号： G06F12/082 , G06F12/0813 , G06F2212/2542
摘要： Methods, systems and computer program products to maintain cache coherency in a System On Chip (SOC) which is part of a distributed shared memory system are described. A local SOC unit that includes a local controller and an on-chip memory is provided. In response to receiving a request from a remote controller of a remote SOC to access a memory location, the local controller determines whether the local SOC has exclusive ownership of the requested memory location, sends data from the memory location if the local SOC has exclusive ownership of the memory location and stores an entry in the on-chip memory that identifies the remote SOC as having requested data from the memory location. The entry specifies whether the request from the remote SOC is for exclusive ownership of the memory location. The entry also includes a field that identifies the remote SOC as the requester. The requested memory location may be external or internal to the local SOC unit.

52. 发明授权

EP2437433B1 MEMORY ACCESS MONITORING METHOD AND DEVICE 有权
标题翻译：存储器访问监视方法和装置
公开(公告)号：EP2437433B1
公开(公告)日：2017-09-06
申请号：EP11750199.9
申请日：2011-04-19
申请人： Huawei Technologies Co., Ltd.
发明人： ZHANG, Xiaofeng , FANG, Fan
IPC分类号： G06F12/02 , G06F12/12 , G06F11/34 , G06F12/122
CPC分类号： G06F12/0284 , G06F11/3466 , G06F12/122 , G06F2201/88 , G06F2201/885 , G06F2212/2542

53. 发明公开

EP3131015A1 MEMORY MIGRATION METHOD AND DEVICE 有权
标题翻译： VERFAHREN UND VORRICHTUNGFÜRSPEICHERMIGRATION
公开(公告)号：EP3131015A1
公开(公告)日：2017-02-15
申请号：EP15840667.8
申请日：2015-06-01
申请人： Huawei Technologies Co., Ltd.
发明人： CHU, Lixing
IPC分类号： G06F12/06
CPC分类号： G06F3/0647 , G06F3/06 , G06F3/0619 , G06F3/064 , G06F3/0644 , G06F3/0683 , G06F9/50 , G06F9/5016 , G06F9/5022 , G06F9/5033 , G06F12/06 , G06F12/0813 , G06F2212/2542
摘要： A memory migration method and device are provided, and relate to the field of computer application technologies. A memory page is combined into a memory block, which reduces a quantity of migrations, and improves CPU utilization. The method includes: receiving, by a first node, a migration instruction sent by a second node (201); sequentially scanning each memory page between a physical address of a start memory page accessed by a target process and a physical address of an end memory page accessed by the target process (202), where the memory page is a memory page accessed by the target process or a memory page accessed by a non-target process; determining whether each memory page meets a block combination condition, and combining a memory page that meets the block combination condition into a corresponding memory block (203); and migrating the corresponding memory block to a memory area of the second node (204).
摘要翻译：提供了一种内存迁移方法和设备，涉及计算机应用技术领域。内存页面被组合成一个内存块，这减少了迁移量，并提高了CPU利用率。该方法包括：由第一节点接收由第二节点（201）发送的迁移指令; 在由目标进程访问的起始存储器页面的物理地址和由目标进程（202）访问的结束存储器页面的物理地址之间顺序地扫描每个存储器页面，其中存储器页面是目标进程访问的存储器页面或非目标进程访问的内存页; 确定每个存储器页是否满足块组合条件，以及将满足块组合条件的存储器页组合到相应的存储块（203）中; 以及将所述对应的存储器块迁移到所述第二节点（204）的存储器区域。

54. 发明公开

EP3101548A1 PARALLEL COMPUTER, MIGRATION PROGRAM AND MIGRATION METHOD 审中-公开
标题翻译：和平协调员，移民安置移民协调员
公开(公告)号：EP3101548A1
公开(公告)日：2016-12-07
申请号：EP16170797.1
申请日：2016-05-23
申请人： FUJITSU LIMITED
发明人： NINOMIYA, Atsushi
IPC分类号： G06F12/08 , G06F9/48
CPC分类号： G06F3/0605 , G06F3/0647 , G06F3/0673 , G06F9/485 , G06F12/0813 , G06F12/0815 , G06F12/084 , G06F12/0842 , G06F2212/1024 , G06F2212/2542 , G06F2212/62
摘要： A parallel computer includes a first node and a second node, each including a memory having a plurality of memory areas and a cache memory, and a processing unit that acquires a first group of index levels of the cache memory, the first group of index levels corresponding with addresses of first plurality of memory areas storing data accessed by a job in the first node, when continuing an execution of the job by migrating the job carried out on the first node to the second node, judges whether or not the second node has second plurality of memory areas that are a usable state corresponding to a second group of index levels that has same as or relative position relation with the first group of index levels, and relocates the data to the second plurality of memory areas when the second node has the second plurality of memory areas.
摘要翻译：并行计算机包括第一节点和第二节点，每个包括具有多个存储区域的存储器和高速缓冲存储器，以及处理单元，其获取高速缓冲存储器的第一组索引级别，第一组索引级别对应于当通过将在第一节点上执行的作业迁移到第二节点来继续执行作业时，存储由第一节点中的作业访问的数据的第一多个存储区域的地址，判断第二节点是否具有第二多个存储区域，其是对应于与第一组索引级别具有相同或相对位置关系的第二组索引级别的可用状态，并且当第二节点具有数据时将数据重新定位到第二多个存储区域第二多个存储区域。

55. 发明公开

EP2909728A1 MULTISLOT LINK LAYER FLIT 审中-公开
标题翻译：多槽链接层FLIT
公开(公告)号：EP2909728A1
公开(公告)日：2015-08-26
申请号：EP13848818.4
申请日：2013-03-16
申请人： Intel Corporation
发明人： WILLEY, Jeff , BLANKENSHIP, Robert G. , SWANSON, Jeffrey C. , SAFRANEK, Robert J.
IPC分类号： G06F13/14 , G06F13/38
CPC分类号： G06F13/22 , G06F1/3287 , G06F8/71 , G06F8/73 , G06F8/77 , G06F9/30145 , G06F9/44505 , G06F9/466 , G06F11/1004 , G06F12/0806 , G06F12/0808 , G06F12/0813 , G06F12/0815 , G06F12/0831 , G06F12/0833 , G06F13/4022 , G06F13/4068 , G06F13/4221 , G06F13/4282 , G06F13/4286 , G06F13/4291 , G06F2212/1016 , G06F2212/2542 , G06F2212/622 , H04L9/0662 , H04L12/4641 , H04L45/74 , H04L49/15 , Y02D10/13 , Y02D10/14 , Y02D10/151 , Y02D10/40 , Y02D10/44 , Y02D30/30
摘要： Re-initialization of a link can take place without termination of the link, where the link includes, a transmitter and a receiver are to be coupled to each lane in the number of lanes, and re-initialization of the link is to include transmission of a pre-defined sequence on cach of the lanes.
摘要翻译：事务处理数据被识别，并且生成微片以包括三个或更多个插槽以及用作两个或更多个插槽中的任何一个插槽的扩展的浮动字段。至少部分地基于三个或更多个时隙，将所述微片通过串行数据链路发送到用于处理的设备。

56. 发明公开

EP2869208A1 METHOD FOR CONSTRUCTING MULTIPROCESSOR SYSTEM WITH NODE HAVING A PLURALITY OF CACHE UNIFORMITY DOMAINS 审中-公开
标题翻译：一种用于生产多处理器系统与多个缓存GLEICHFÖRMIGKEITSDOMÄNEN结
公开(公告)号：EP2869208A1
公开(公告)日：2015-05-06
申请号：EP13865541.0
申请日：2013-01-22
申请人： Inspur Electronic Information Industry Co., Ltd.
发明人： WANG, Endong , HU, Leijun , CHEN, Jicheng , ZHANG, Dong , GONG, Weifeng , ZHANG, Feng
IPC分类号： G06F15/167
CPC分类号： G06F12/0822 , G06F12/082 , G06F12/0826 , G06F15/17368 , G06F2212/1016 , G06F2212/1048 , G06F2212/2542 , G06F2212/622
摘要： A method for building a multi-processor system with nodes having multiple cache coherency domains. In this system, a directory built in a node controller needs to include processor domain attribute information, and the information can be acquired by configuring cache coherency domain attributes of ports of the node controller connected to processors. In the disclosure herein, the node controller can support the multiple physical cache coherency domains in a node.
摘要翻译：一种用于构建具有多个高速缓存一致性域节点的多处理器系统的方法。在这个系统中，建立在一个节点控制器的目录需要包括处理器域属性信息，并且可以通过配置连接到处理器节点控制器的端口的高速缓存一致性域的属性来获取的信息。在本公开中，节点控制器可以支持在一个节点中的多个物理缓存一致性域。

57. 发明授权

EP2608044B1 Information processing apparatus and memory access method 有权
标题翻译：信息处理装置和存储器访问方法
公开(公告)号：EP2608044B1
公开(公告)日：2014-11-26
申请号：EP12187771.6
申请日：2012-10-09
申请人： FUJITSU LIMITED
发明人： Koinuma, Hideyuki , Okada, Seishi , Sugizaki, Go
IPC分类号： G06F12/02 , G06F12/14 , G06F12/10
CPC分类号： G06F12/0284 , G06F12/1072 , G06F12/1441 , G06F2212/2542

58. 发明公开

EP2437433A4 MEMORY ACCESS MONITORING METHOD AND DEVICE 有权
标题翻译：存储器访问控制和设备
公开(公告)号：EP2437433A4
公开(公告)日：2012-08-22
申请号：EP11750199
申请日：2011-04-19
申请人： HUAWEI TECH CO LTD
发明人： ZHANG XIAOFENG , FANG FAN
IPC分类号： G06F12/02 , G06F11/34 , G06F12/12
CPC分类号： G06F12/0284 , G06F11/3466 , G06F12/122 , G06F2201/88 , G06F2201/885 , G06F2212/2542

59. 发明公开

EP2437433A2 MEMORY ACCESS MONITORING METHOD AND DEVICE 有权
标题翻译： SPEICHERZUGANGSÜBERWACHUNGSVERFAHRENUND -VORRICHTUNG
公开(公告)号：EP2437433A2
公开(公告)日：2012-04-04
申请号：EP11750199.9
申请日：2011-04-19
申请人： Huawei Technologies Co., Ltd.
发明人： ZHANG, Xiaofeng , FANG, Fan
IPC分类号： H04L12/24
CPC分类号： G06F12/0284 , G06F11/3466 , G06F12/122 , G06F2201/88 , G06F2201/885 , G06F2212/2542
摘要： A memory access monitoring method and a memory access monitoring method device are disclosed, wherein the memory access monitoring method comprises: performing coarse grain monitoring on local memory pages, if a hot page with coarse grain monitoring exists in the local memory pages, requesting an operating system to perform an optimized migration for the content of the hot page, and if a half hot page with coarse grain monitoring exists in the local memory pages, initiating fine grain monitoring to the half hot page; and performing fine grain monitoring on the half hot page, if a hot area with fine grain monitoring exists in the half hot page, requesting the operating system to perform an optimized migration for the content of the hot area. The combination of coarse grain monitoring and fine grain monitoring is employed in the embodiments of the present invention, so as to reduce the number of counters required by memory access monitoring, which can effectively recognize the cross-nodes hot area which needs to be optimized and improve the memory access optimization efficiency in non-uniform memory access (NUMA) architecture.
摘要翻译：本发明公开了一种存储器访问监视方法和存储器存取监视方法装置，其中存储器访问监视方法包括：对本地存储器页面进行粗粒度监视，如果在本地存储器页面中存在具有粗粒度监视的热页面，请求操作系统对热页面的内容执行优化迁移，如果本地内存页面中存在粗粒度监控的半热页面，则对半热页面启动细粒度监控; 并在半热页面上执行细粒度监控，如果在半热页面中存在具有细粒度监视的热区域，则请求操作系统对热区域的内容执行优化迁移。在本发明的实施例中采用粗粒监测和细粒监测的组合，以减少存储器访问监视所需的计数器数量，这可以有效地识别需要优化的跨节点热区域，提高了非均匀内存访问（NUMA）体系结构中的内存访问优化效率。

60. 发明公开

EP2433227A1 SCALABLE INDEXING IN A NON-UNIFORM ACCESS MEMORY 有权转让
标题翻译：非均匀访问存储器中的可扩展索引
公开(公告)号：EP2433227A1
公开(公告)日：2012-03-28
申请号：EP10731653.1
申请日：2010-06-25
申请人： Simplivity Corporation
发明人： BOWDEN, Paul , BEAVERSON, Arthur, J.
IPC分类号： G06F17/30
CPC分类号： G06F12/1054 , G06F12/0246 , G06F12/0864 , G06F12/0875 , G06F12/1408 , G06F17/30097 , G06F17/30949 , G06F17/30952 , G06F2212/2542 , G06F2212/402 , G06F2212/452 , G06F2212/502 , G06F2212/6032 , G06F2212/7211
摘要： Method and apparatus for constructing an index that scales to a large number of records and provides a high transaction rate. New data structures and methods are provided to ensure that an indexing algorithm performs in a way that is natural (efficient) to the algorithm, while a non-uniform access memory device sees IO (input/output) traffic that is efficient for the memory device. One data structure, a translation table, is created that maps logical buckets as viewed by the indexing algorithm to physical buckets on the memory device. This mapping is such that write performance to non¬ uniform access SSD and flash devices is enhanced. Another data structure, an associative cache is used to collect buckets and write them out sequentially to the memory device as large sequential writes. Methods are used to populate the cache with buckets (of records) that are required by the indexing algorithm. Additional buckets may be read from the memory device to cache during a demand read, or by a scavenging process, to facilitate the generation of free erase blocks.
摘要翻译：用于构建可扩展到大量记录并提供高事务率的索引的方法和设备。提供新的数据结构和方法以确保索引算法以对算法而言自然（高效）的方式执行，而非均匀访问存储器设备看到对存储器设备有效的IO（输入/输出）流量。创建一个数据结构，一个转换表，将由索引算法查看的逻辑存储区映射到存储设备上的物理存储区。这种映射使得写入到非统一访问SSD和闪存设备的性能得到增强。另一种数据结构，即关联缓存用于收集存储桶，并将其按顺序写入存储设备作为大量顺序写入。方法用于使用索引算法所需的存储桶（记录）填充高速缓存。可以在需求读取期间或通过清除过程从存储器设备中读取额外的存储桶以缓存以便于产生自由擦除块。

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