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41. 发明公开

EP0530373A4 CIRCUIT FOR CONVERTING LEVEL 失效
标题翻译：转换电路
公开(公告)号：EP0530373A4
公开(公告)日：1993-12-15
申请号：EP92906920
申请日：1992-03-18
申请人： FUJITSU LIMITED , FUJITSU VLSI LIMITED
发明人： SEKI, TERUO , UKAI, HIROAKI
IPC分类号： H03K19/003 , H03K19/0175
CPC分类号： H03K19/017554 , H03K19/00369 , H03K19/017527

42. 发明公开

EP0520830A3 Apparatus and method for ECL-like signal to CMOS signal conversion 失效
标题翻译：用于ECL信号到CMOS信号转换的装置和方法
公开(公告)号：EP0520830A3
公开(公告)日：1993-03-17
申请号：EP92305946.3
申请日：1992-06-26
申请人： TEXAS INSTRUMENTS INCORPORATED
发明人： Ovens, Kevin M. , Helmick, Robert A.
IPC分类号： H03K19/0175
CPC分类号： H03K19/017527 , H03K19/00369 , H03K19/01721 , H03K19/017518
摘要： In one aspect of the present invention, a converter (30) is provided comprising a capacitive coupling (182, 183) arranged to receive said input signal to be converted, and a conversion circuitry coupled to the capacitive coupling (182, 183) to produce the converted output signal. A biasing circuit (185) is further arranged to facilitate a fast transition in the converted output signal in response to an active transition in the input signal.

43. 发明公开

EP0449567A2 Positive to negative voltage translator circuit and method of operation 失效
标题翻译： Positiv-nach-negativ-Spannungsumsetzerschaltung und Betriebsverfahren。
公开(公告)号：EP0449567A2
公开(公告)日：1991-10-02
申请号：EP91302605.0
申请日：1991-03-26
申请人： TEXAS INSTRUMENTS INCORPORATED
发明人： Ten Eyck, Timothy A.
IPC分类号： G05F1/46 , G05F3/30
CPC分类号： H03K19/00369 , G05F1/462 , G05F3/30 , H03K19/017518
摘要： There is disclosed a circuit 10 and method for converting on/off logic signals from one medium to on/off signals useful in a different medium. The circuit 10 is particularly adapted to translate from positive voltage levels to negative voltage levels. The circuit 10 includes voltage control levels for precisely controlling voltage as a function of temperature, all whille only using positive voltage levels on the conversion circuit.
There is also disclosed a circuit 20 and method for providing bias voltage levels which are precisely controlled as a function of temperature. The circuit 20 is arranged to mix a precise bandgap regulated voltage with a temperature compensated circuit to provide the required output. The temperature compensated circuit is in turn arranged to mimic the temperature sensitive components in the output circuit.
摘要翻译：公开了一种用于将来自一个介质的逻辑信号转换为在不同介质中有用的开/关信号的电路10和方法。电路10特别适于从正电压电平转换为负电压电平。电路10包括用于精确控制作为温度的函数的电压的电压控制电平，所有这些电平仅在转换电路上使用正电压电平。还公开了一种用于提供作为温度的函数精确控制的偏置电压电平的电路20和方法。电路20被布置成将精确的带隙调节电压与温度补偿电路混合以提供所需的输出。温度补偿电路依次布置成模拟输出电路中的温度敏感元件。

44. 发明授权

EP0207962B1 TRI-STATE DRIVER CIRCUIT 有权
标题翻译：三态驱动电路
公开(公告)号：EP0207962B1
公开(公告)日：1990-10-10
申请号：EP86900466.3
申请日：1985-12-06
申请人： AT&T Corp.
发明人： TUHY, Frank, Philip, Jr.
IPC分类号： H03K19/082 , H03K19/013 , H03K19/00
CPC分类号： H03K19/013 , H03K19/00369 , H03K19/0826
摘要： A single chip, bipolar logic circuit receives input signals in a differential amplifier or comparator stage (54, 56) coupled, without saturation, by differential current mirrors (95, 97) to drive an output stage (74, 82) of the push-pull variety. Various circuit arrangements are included to keep other bipolar transistors out of their saturation operating regions, and master transistors (92, 94) of the current mirror are provided with trickle bias when in the opening state to hold them at turn-on threshold for fast response to changes in state of the digital signals.

45. 发明公开

EP0184875A1 Adaptive electronic buffer amplifier system 有权转让
标题翻译：适应电力Pufferverstärkersystem。
公开(公告)号：EP0184875A1
公开(公告)日：1986-06-18
申请号：EP85201894.4
申请日：1985-11-19
申请人： Philips Electronics N.V.
发明人： Huizer, Cornelis Marinus
IPC分类号： H03K19/00 , H03K17/14 , H03K5/02
CPC分类号： H03K19/00369 , H03K5/02 , H03K17/14
摘要： An adaptive electronic buffer system in which a set circuit (10) generates logic set signals for the buffer circuits (20).
Parallel sub-buffers are switched on or off by the set signals, so that the specified charging and discharging times of the output (22) can be achieved. This setting compensates for the manufacturing process variations and operating conditions (temperature, supply voltage) of the buffer circuits (20). The spread in the output conductance is reduced, thus reducing the risk of fast current variations, inductive voltage peaks and the associated loss of data.
摘要翻译：一种自适应电子缓冲器系统，其中设置电路（10）产生用于缓冲电路（20）的逻辑设置信号。平行子缓冲器通过设定信号被接通或关断，从而可以实现输出（22）的规定的充电和放电时间。该设置补偿缓冲电路（20）的制造工艺变化和工作条件（温度，电源电压）。输出电导的扩展减少，从而降低快速电流变化，感应电压峰值和相关联的数据丢失的风险。

46. 发明公开

EP4427337A1 LEAKAGE REDUCTION AND BIASING CIRCUITS 审中-实审
公开(公告)号：EP4427337A1
公开(公告)日：2024-09-11
申请号：EP23707519.7
申请日：2023-01-20
申请人： Google LLC
发明人： ZHANG, Tong , ABO, Andrew , VANDERHAEGEN, Johan Peter
IPC分类号： H03K19/003
CPC分类号： H03K19/00369 , H03K19/00384

47. 发明公开

EP3014768A4 DELAY CIRCUIT INDEPENDENT OF SUPPLY VOLTAGE 审中-公开
标题翻译：独立供电延迟电路
公开(公告)号：EP3014768A4
公开(公告)日：2017-02-22
申请号：EP14818603
申请日：2014-06-25
申请人： ESS TECH INC
发明人： MALLINSON A MARTIN
IPC分类号： H03K5/15 , H03H11/26 , H03K5/133 , H03K5/14 , H03K19/003 , H03K19/0185
CPC分类号： H03K19/00315 , H03K5/133 , H03K5/14 , H03K5/15046 , H03K19/00361 , H03K19/00369 , H03K19/018521

48. 发明公开

EP3053269A1 PREVENTING TIMING VIOLATIONS 有权转让
标题翻译： VERHINDERUNG VONZEITÜBERSCHREITUNGEN
公开(公告)号：EP3053269A1
公开(公告)日：2016-08-10
申请号：EP14780481.9
申请日：2014-10-02
申请人： Aalto University Foundation , Teknologian Tutkimuskeskus VTT
发明人： MÄKIPÄÄ, Jani , KOSKINEN, Lauri , TURNQUIST, Matthew , HIIENKARI, Markus
IPC分类号： H03K5/19 , G06F1/04 , H03K19/003
CPC分类号： H03K19/00369 , G06F1/04 , G06F1/06 , G06F1/08 , H03K5/06 , H03K5/19
摘要： An apparatus, comprising a clock adapted to provide a clock signal alternating with a cycle between a first level and a second level if a timing violation is not detected; a first latch adapted to be clocked such that it passes a first signal when the clock signal is at the first level; a second combinational logic adapted to output a second signal based on the first signal passed through the first latch; a second latch adapted to be clocked such that it passes the second signal when the clock signal is at the second level; a detecting means adapted to detect the timing violation of at least one of the first signal and of the second signal; a time stretching means adapted to stretch, if the timing violation is detected, the clock such that the clock alternates between the first level and the second level with a delay.
摘要翻译：一种装置，包括适于在未检测到定时违反时提供与第一电平和第二电平之间的周期交替的时钟信号的时钟; 适于被计时的第一锁存器，使得当所述时钟信号处于所述第一电平时，所述第一锁存器通过第一信号; 第二组合逻辑，适于基于通过所述第一锁存器的所述第一信号输出第二信号; 适于被计时的第二锁存器，使得当所述时钟信号处于所述第二电平时，所述第二锁存器通过所述第二信号; 检测装置，其适于检测所述第一信号和所述第二信号中的至少一个的定时违反; 时间延伸装置，适于在检测到定时违反的情况下拉伸时钟，使得时钟以延迟在第一电平和第二电平之间交替。

49. 发明公开

EP2919262A1 Fault detection assembly 有权
标题翻译： Fehlererkennungsanordnung
公开(公告)号：EP2919262A1
公开(公告)日：2015-09-16
申请号：EP14159970.4
申请日：2014-03-14
申请人： EM Microelectronic-Marin SA
发明人： Plavec, Lubomir , Lukes, Zdenek
IPC分类号： H01L21/66 , H03K19/003
CPC分类号： G01R31/2621 , H01L22/34 , H01L27/0266 , H03K19/00315 , H03K19/00369
摘要： The present invention relates to a fault detection assembly of an integrated circuit (10) having a supply port (12), an input port (14) and a ground port (16). The fault detection assembly comprises a first diode (20) connected with one end to the supply port (12) and connected with the other end to the input port (14), a second diode (24) connected with one end to the input port (14) and connected with the other end to the ground port (16), at least a first fault detection transistor (30, 32) of MOS type. At least one of first and second diodes (20, 24) comprises a first diode-connected MOS transistor (22, 26) whose gate is connected to the gate of the first fault detection transistor (30, 32).
摘要翻译：本发明涉及具有供应端口（12），输入端口（14）和接地端口（16）的集成电路（10）的故障检测组件。所述故障检测组件包括：第一二极管（20），其一端连接到所述供应端口（12）并与另一端连接到所述输入端口;第二二极管（24），其一端连接到所述输入端口（14）并且与另一端连接到接地端口（16），至少是MOS型的第一故障检测晶体管（30,32）。第一和第二二极管（20,24）中的至少一个包括其栅极连接到第一故障检测晶体管（30,32）的栅极的第一二极管连接的MOS晶体管（22,26）。

50. 发明公开

EP2685632A3 Thermal control apparatus and methodology 有权转让
标题翻译：热控制装置和方法
公开(公告)号：EP2685632A3
公开(公告)日：2014-05-21
申请号：EP13171669.8
申请日：2013-06-12
申请人： APPLE INC.
发明人： Lin, Jim J. , Kattel, Kiran B.
IPC分类号： H03K19/003 , G06F1/20
CPC分类号： G06F1/206 , G06F1/324 , G06F1/3296 , H03K19/00369 , Y02D10/126
摘要： Various embodiments of a thermal control methodology and apparatus are disclosed. In one embodiment, an integrated circuit includes one or more thermal sensors, comparison circuitry, and control circuitry. The comparison circuitry is configured to receive temperature readings from the one or more thermal sensors. The control circuitry is configured to reduce a performance level of one or more controlled subsystems responsive to the comparison circuitry determining that at least one temperature reading from the one or more thermal sensors exceeds one of one or more threshold values. A software-based thermal control mechanism may also execute concurrently with the apparatus.

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