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41. 发明公开

EP1851797A1 DEVICE AND METHOD FOR FABRICATING DOUBLE-SIDED SOI WAFER SCALE PACKAGE WITH THROUGH VIA CONNECTIONS 有权
标题翻译：装置及其制造方法的双面围封对SOI晶片级带有通路
公开(公告)号：EP1851797A1
公开(公告)日：2007-11-07
申请号：EP05807945.0
申请日：2005-11-03
申请人： International Business Machines Corporation
发明人： CHEN, Howard, Hao , HSU, Louis, Lu-Chen
IPC分类号： H01L23/48 , H01L25/065 , H01L25/18 , H01L21/768 , H01L29/06
CPC分类号： H01L21/76898 , H01L23/481 , H01L24/05 , H01L24/94 , H01L25/0652 , H01L25/18 , H01L2221/68345 , H01L2221/68363 , H01L2224/05009 , H01L2224/0557 , H01L2224/06181 , H01L2224/14181 , H01L2224/16 , H01L2224/16146 , H01L2224/81191 , H01L2224/81192 , H01L2224/94 , H01L2924/01078 , H01L2924/01079 , H01L2924/10253 , H01L2924/13091 , H01L2924/14 , H01L2924/1461 , H01L2924/15153 , H01L2924/1517 , H01L2924/16195 , H01L2924/00 , H01L2224/11 , H01L2224/81
摘要： A semiconductor package includes an SOI wafer having a first side including an integrated circuit system, and a second side, opposite the first side, forming at least one cavity. At least one chip or component is placed in the cavity. An optical through via is formed through a buried oxide which optically connects the chip(s) to the integrated circuit system.

42. 发明公开

EP1684339A2 Method of manufacturing semiconductor device and method of treating electrical connection section 审中-公开
标题翻译：一种用于生产治疗的电连接部的半导体装置和制造方法的工序
公开(公告)号：EP1684339A2
公开(公告)日：2006-07-26
申请号：EP06001010.5
申请日：2006-01-18
申请人： SEIKO EPSON CORPORATION
发明人： Nakayama, Hirohisa , Sato, Shiro , Shoji, Masanobu , Nosaka, Hitoshi
IPC分类号： H01L21/60
CPC分类号： H05K3/3489 , H01L21/4853 , H01L21/563 , H01L23/49816 , H01L24/03 , H01L24/05 , H01L24/06 , H01L24/11 , H01L24/13 , H01L24/81 , H01L24/83 , H01L2224/02166 , H01L2224/02331 , H01L2224/0236 , H01L2224/02377 , H01L2224/02381 , H01L2224/0239 , H01L2224/0381 , H01L2224/0391 , H01L2224/0401 , H01L2224/05624 , H01L2224/06131 , H01L2224/06155 , H01L2224/11 , H01L2224/1191 , H01L2224/13 , H01L2224/13022 , H01L2224/13099 , H01L2224/131 , H01L2224/13111 , H01L2224/13144 , H01L2224/16 , H01L2224/16225 , H01L2224/2929 , H01L2224/293 , H01L2224/32225 , H01L2224/73204 , H01L2224/81801 , H01L2224/83851 , H01L2924/00 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01022 , H01L2924/01023 , H01L2924/01024 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/0105 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01084 , H01L2924/014 , H01L2924/09701 , H01L2924/14 , H01L2924/15311 , H01L2924/15787 , H01L2924/19041 , H01L2924/19043 , H01L2924/00014
摘要： A method of manufacturing a semiconductor device includes: applying a paste containing acid to an electrical connection section which is electrically connected with a semiconductor substrate; removing the paste from the electrical connection section by washing the electrical connection section; and providing a conductive material to the electrical connection section.
摘要翻译：一种制造半导体器件的方法包括：将糊含酸在电连接部分中的所有这是与一个半导体衬底电连接; 通过洗涤电连接部去除电连接部的糊状物; 和提供导电材料的电连接部。

43. 发明公开

EP1551211A4 SOLDER-COATED BALL AND METHOD FOR MANUFACTURE THEREOF, AND METHOD FOR FORMING SEMICONDUCTOR INTERCONNECTING STRUCTURE 有权
标题翻译：焊料包覆球和方法形成半导体连接结构PRODUCING和方法
公开(公告)号：EP1551211A4
公开(公告)日：2005-12-07
申请号：EP03798471
申请日：2003-09-24
申请人： NEOMAX MATERIALS CO LTD
发明人： KONDO MASUO , KIKUI FUMIAKI
IPC分类号： B23K35/02 , H01L23/485 , H01L23/498 , H05K3/34 , H01L23/12
CPC分类号： H05K3/3436 , B23K35/0244 , H01L23/49816 , H01L24/11 , H01L24/13 , H01L2224/05001 , H01L2224/05023 , H01L2224/0508 , H01L2224/05147 , H01L2224/05155 , H01L2224/05568 , H01L2224/05644 , H01L2224/11 , H01L2224/11334 , H01L2224/13 , H01L2224/13099 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01018 , H01L2924/01019 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01322 , H01L2924/014 , H01L2924/15747 , H01L2924/15787 , H05K3/3463 , H05K2201/10234 , Y02P70/613 , H01L2924/00 , H01L2924/00014
摘要： A solder-coated ball (50) which has a core (2) having the shape of a ball and, provided around the core (2), a solder layer (4) comprising Sn and Ag, wherein the solder layer (4) contains water in an amount of 100 μl/g or less in terms of the steam in the standard state.

44. 发明公开

EP1470583A4 CHIP AND WAFER INTEGRATION PROCESS USING VERTICAL CONNECTIONS 审中-公开
标题翻译：与垂直连接芯片和外延片的一体化进程
公开(公告)号：EP1470583A4
公开(公告)日：2005-08-03
申请号：EP02789958
申请日：2002-11-26
申请人： IBM
发明人： POGGE BERNHARD H , YU ROY , PRASAD CHANDRIKA , NARAYAN CHANDRASEKHAR
IPC分类号： H01L23/12 , H01L21/68 , H01L21/768 , H01L23/48 , H01L23/485 , H01L23/525 , H01L25/065 , H01L25/07 , H01L25/18
CPC分类号： H01L24/10 , H01L21/6835 , H01L21/76877 , H01L21/76898 , H01L23/481 , H01L23/525 , H01L24/13 , H01L24/81 , H01L25/0652 , H01L2224/03002 , H01L2224/0401 , H01L2224/05155 , H01L2224/05166 , H01L2224/05184 , H01L2224/0557 , H01L2224/05572 , H01L2224/05644 , H01L2224/06181 , H01L2224/13 , H01L2224/13099 , H01L2224/16145 , H01L2224/17181 , H01L2224/81005 , H01L2224/94 , H01L2924/01004 , H01L2924/01006 , H01L2924/01022 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/01039 , H01L2924/01057 , H01L2924/01061 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/014 , H01L2924/10329 , H01L2924/12042 , H01L2924/14 , H01L2924/15787 , H01L2224/11 , H01L2224/03 , H01L2924/00 , H01L2924/00014 , H01L2924/013
摘要： A process is described for semiconductor device integration at chip level or wafer level, in which vertical connections are formed through a substrate (1). A metallized feature (2) is formed in the top surface of a substrate, and a handling plate (35) is attached to the substrate. The substrate is then thinned at the bottom surface thereof to expose the bottom of the feature, to form a conducting through-via (20). The substrate may comprise a chip (44) having a device (30), e.g. a PE chip. The plate may be a wafer (65) attached to the substrate using a vertical stud/via interconnection. The substrate and plate may each have devices (30,60) fabricated therein, so that the process provides vertical wafer-level integration of the devices.

45. 发明公开

EP1556904A2 VERFAHREN ZUM HERSTELLEN EINER LEUCHTDIODEN-LICHTQUELLE MIT LUMINESZENZ-KONVERSIONSELEMENT 有权转让
标题翻译： VERFAHREN ZUM HERSTELLEN EINER LEUCHTDIODEN-LICHTQULELE MIT LUMINESZENZ-KONVERSIONSELEMENT
公开(公告)号：EP1556904A2
公开(公告)日：2005-07-27
申请号：EP03776808.2
申请日：2003-10-21
申请人： Osram Opto Semiconductors GmbH
发明人： BRAUNE, Bert , BRUNNER, Herbert
IPC分类号： H01L33/00
CPC分类号： H01L33/505 , H01L33/38 , H01L2224/11 , H01L2933/0016 , H01L2933/0041
摘要： The invention relates to a method for producing a light source provided with electroluminescent diodes, in particular mixed colour diodes. The inventive method consists in transforming at least one part of primary radiation emitted a chip by means of luminescence conversion. The inventive chip comprises a front electric contact (in terms of a surface oriented towards a radiation emission) and a luminescence conversion material applied thereto in the form of a thin film. Prior to coating, the front electric contact is made higher by the application of a conductive material to the surface thereof. The inventive method makes it possible to adjust in a target manner a defined chromatic localisation controlling said chromatic localisation (IEC chromaticity diagram) and reducing the layer of the luminescence conversion material. Said method is convenient, in particular for simultaneously producing several light sources provided with electrolumeniscent diodes from the plurality of similar chips in a section composite substrate.
摘要翻译：本发明描述了一种用于制造发光二极管（LED）光源的方法，特别地包括混合彩色LED，其中由芯片发射的主要辐射的至少一部分通过发光转换而变换。所述芯片包括前表面（即面向辐射方向的一侧）电接触，其表面以薄层的形式施加发光转换材料。在涂覆之前，通过将导电材料施加到电接触表面来提高前侧电接触。该方法通过监视颜色坐标（IEC色度图）和稀释发光转换材料层来使选择性地调整特定色坐标。此外，该方法特别适用于从晶片复合材料中的多个类似的芯片同时制造多个LED光源。

46. 发明公开

EP1551211A1 SOLDER-COATED BALL AND METHOD FOR MANUFACTURE THEREOF, AND METHOD FOR FORMING SEMICONDUCTOR INTERCONNECTING STRUCTURE 有权
标题翻译：焊料包覆球和方法形成半导体连接结构PRODUCING和方法
公开(公告)号：EP1551211A1
公开(公告)日：2005-07-06
申请号：EP03798471.3
申请日：2003-09-24
申请人： Neomax Materials Co., Ltd.
发明人： KONDO, Masuo , KIKUI, Fumiaki
IPC分类号： H05K3/34 , H01L23/12
CPC分类号： H05K3/3436 , B23K35/0244 , H01L23/49816 , H01L24/11 , H01L24/13 , H01L2224/05001 , H01L2224/05023 , H01L2224/0508 , H01L2224/05147 , H01L2224/05155 , H01L2224/05568 , H01L2224/05644 , H01L2224/11 , H01L2224/11334 , H01L2224/13 , H01L2224/13099 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01018 , H01L2924/01019 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01322 , H01L2924/014 , H01L2924/15747 , H01L2924/15787 , H05K3/3463 , H05K2201/10234 , Y02P70/613 , H01L2924/00 , H01L2924/00014
摘要： A solder ball 50 according to the present invention includes a spherical core 2 and a solder layer 4, which includes Sn and Ag and which is provided so as to wrap the core 2 up. The amount of water contained in the solder layer 4 is 100 µl/g or less when represented by the amount of water vapor in standard conditions.
摘要翻译：焊球50张雅丁到本发明包括被设置为包裹所述芯2向上的球形芯2和焊料层4，其包括Sn和Ag和全部。包含在焊料层4的水的量为100 亩升/克或更小。当通过在标准条件下的水蒸汽的量代表。

47. 发明公开

EP1109215A3 Apparatus and method for solder bump inspection 审中-公开
标题翻译：设备和方法Lotkugelinspektion
公开(公告)号：EP1109215A3
公开(公告)日：2005-06-22
申请号：EP00126574.3
申请日：2000-12-12
申请人： SHINKO ELECTRIC INDUSTRIES CO. LTD.
发明人： Murayama, Kei, Shinko Electric Ind. Co., Ltd. , Higashi, Mitsutoshi, Shinko Electric Ind. Co. Ltd.
IPC分类号： G01N21/956 , G01N21/88 , H01L21/60 , H01L21/66
CPC分类号： G01B11/0608 , H01L22/12 , H01L2224/11
摘要： A bump inspection apparatus for inspecting shapes of a plurality of bumps each having a planar top portion, on an inspection object, comprising an illumination optical system for illuminating the top portions with a vertical parallel pencil of light through a telecentric optical system, an observation optical system using a telecentric optical system having an optical axis thereof in conformity with that of the illumination optical system, an observation portion for observing the images of the top portions through the observation optical system in a predetermined range of the inspection object, and a processing portion for analyzing the shapes of the bumps on the basis of the images of the top portions by the observation portion, wherein the processing portion includes analyzing means for analyzing the areas of the planar top portions for the individual bumps and judging means for judging whether or not the rears of the top portions are within a predetermined range. A bump inspection method using this apparatus is described, too.

48. 发明公开

EP1542279A2 Semiconductor device and the method of producing the same 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：EP1542279A2
公开(公告)日：2005-06-15
申请号：EP04292958.8
申请日：2004-12-13
申请人： SONY CORPORATION
发明人： Yamagata, Osamu, Sony Corporation
IPC分类号： H01L23/31 , H01L23/528 , H01L23/00 , H01L23/485
CPC分类号： H01L24/10 , H01L23/3114 , H01L23/5283 , H01L23/562 , H01L24/13 , H01L2224/05001 , H01L2224/05008 , H01L2224/05023 , H01L2224/05024 , H01L2224/05147 , H01L2224/05166 , H01L2224/05647 , H01L2224/13 , H01L2224/13022 , H01L2224/131 , H01L2224/94 , H01L2924/00013 , H01L2924/01005 , H01L2924/01006 , H01L2924/01021 , H01L2924/01022 , H01L2924/01029 , H01L2924/01033 , H01L2924/01075 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/30105 , H01L2924/30107 , H01L2224/13099 , H01L2224/11 , H01L2924/00 , H01L2924/00014
摘要： A SiP type semiconductor device and a method of producing the same wherein curvature of a wafer is suppressed in the production steps, workability does not decline, and high throughput can be attained is provided. An insulation layer is formed by stacking a plurality of resin layers (20 to 23) on a semiconductor substrate (10a), wiring layers (30 to 35) are formed by being buried in the insulation layer so as to be connected to an electronic circuit, an insulating buffer layer (24) for buffering a stress generated at the time of being mounted on a board is formed on the insulation layer, and a conductive post (36) is formed through the buffer layer and connected to the wiring layer, and a projecting electrode (37) is formed projecting from a surface of the buffer layer and connected to the conductive post; and resin layers (20 to 23) composing the insulation layer are formed on a region excluding an outer circumferential portion of the semiconductor substrate, and the buffer layer is formed on a region not exceeding a formation region of a resin layer having the largest area among the plurality of resin layers.
摘要翻译：一种SiP型半导体器件及其制造方法，其中在制造步骤中晶片的曲率被抑制，可加工性不下降，并且可以获得高产量。通过在半导体衬底（10a）上堆叠多个树脂层（20至23）形成绝缘层，通过埋入绝缘层中形成布线层（30至35）以连接至电子电路中，在绝缘层上形成用于缓冲安装在基板上时产生的应力的绝缘缓冲层（24），并且形成穿过缓冲层并连接到布线层的导电柱（36），并且突起电极（37）形成为从缓冲层的表面突出并连接到导电柱; 在除了所述半导体基板的外周部以外的区域形成构成所述绝缘层的树脂层（20〜23），在不超过所述半导体基板中的面积最大的树脂层的形成区域的区域形成所述缓冲层多个树脂层。

49. 发明公开

EP1517367A2 Resin composition for encapsulating semiconductor device 审中-公开
标题翻译： Harzzusammensetzung zum Verkapseln von Halbleitern
公开(公告)号：EP1517367A2
公开(公告)日：2005-03-23
申请号：EP04022039.4
申请日：2004-09-16
申请人： Nitto Denko Corporation
发明人： Noro, Hiroshi
IPC分类号： H01L23/28 , H01L21/56
CPC分类号： H01L24/27 , C08G59/621 , H01L21/563 , H01L23/293 , H01L24/29 , H01L2224/16225 , H01L2224/27003 , H01L2224/274 , H01L2224/32225 , H01L2224/73104 , H01L2224/73203 , H01L2224/73204 , H01L2224/83191 , H01L2224/94 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01019 , H01L2924/01021 , H01L2924/01027 , H01L2924/01029 , H01L2924/01032 , H01L2924/01033 , H01L2924/0104 , H01L2924/01047 , H01L2924/0105 , H01L2924/01057 , H01L2924/01058 , H01L2924/01072 , H01L2924/01074 , H01L2924/01079 , H01L2924/01082 , H01L2924/12042 , H01L2924/15787 , Y10T428/31511 , Y10T428/31515 , Y10T428/31522 , H01L2924/00 , H01L2224/11 , H01L2224/27
摘要： A resin composition usable for encapsulating a semiconductor, comprising (A) an epoxy resin having two or more epoxy groups in one molecule; (B) a curing agent; and (C) inorganic composite oxide particles constituted by silicon dioxide and at least one metal oxide selected from the group consisting of oxides of metal atoms belonging to Group III and Group IV of the Periodic Table excluding silicon; a semiconductor device comprising a wiring circuit board, a semiconductor element, and the above resin composition; and a method for manufacturing a semiconductor device comprising the steps of adhering a resin sheet comprising the resin composition of claim 1 and a stripping sheet to a semiconductor circuit side of a bump-mounting wafer, removing the stripping sheet leaving only the resin composition to the wafer, and cutting the wafer into individual chips.
摘要翻译：一种可用于封装半导体的树脂组合物，其包含（A）在一个分子中具有两个或更多个环氧基的环氧树脂; （B）固化剂; 和（C）由二氧化硅和至少一种金属氧化物构成的无机复合氧化物颗粒，所述金属氧化物选自属于不含硅的周期表第III族和第IV族的金属原子的氧化物; 包括布线电路板，半导体元件和上述树脂组合物的半导体器件; 以及制造半导体器件的方法，包括以下步骤：将包含权利要求1的树脂组合物的树脂片和剥离片粘附到凸块安装晶片的半导体电路侧，将仅剥离树脂组合物的剥离片除去晶片，并将晶片切割成单个芯片。

50. 发明公开

EP1341991A2 LASER SEPARATED DIE WITH TAPERED SIDEWALLS FOR IMPROVED LIGHT EXTRACTION 审中-公开
标题翻译： BY激光器芯片分离了具有FOR LIGHT降的改进锥形侧壁
公开(公告)号：EP1341991A2
公开(公告)日：2003-09-10
申请号：EP01987030.2
申请日：2001-11-16
申请人： Emcore Corporation
发明人： ELIASHEVICH, Ivan , GOTTFRIED, Mark
IPC分类号： F01L1/00
CPC分类号： H01L33/20 , B23K26/073 , B23K26/40 , B23K2201/40 , B23K2203/50 , H01L21/78 , H01L33/0095 , H01L2224/05568 , H01L2224/05573 , H01L2224/0558 , H01L2224/11 , H01L2924/10158 , Y10S438/948 , H01L2224/05644 , H01L2924/00014 , H01L2224/05666
摘要： A method for separating individual optoelectronic devices, such as LEDs, from a wafer includes directing a laser beam (256) having a width toward a major surface of the semiconductor wafer. The laser beam has an image with a first portion of a first energy per unit width and a second portion of a second energy per unit width less than the first energy. The laser beam image (266) cuts into the first major surface of the semiconductor wafer to produce individual devices.

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