专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

41. 发明公开

EP1313029A1 System having configurable interfaces for flexible system configurations 有权
标题翻译： Multicomputersystem mit konfigurierbaren Schnittstellenfürflexible Systemkonfigurationen
公开(公告)号：EP1313029A1
公开(公告)日：2003-05-21
申请号：EP02025687.1
申请日：2002-11-20
申请人： Broadcom Corporation
发明人： Sano, Barton J.
IPC分类号： G06F15/78
CPC分类号： G06F12/0831
摘要： An apparatus includes a plurality of memories, a plurality of systems, and a switch interface circuit. Each of the plurality of systems includes a memory controller coupled to a respective one of the plurality of memories. Additionally, each of the plurality of systems is coupled to at least one other one of the plurality of systems. Each of the plurality of systems further includes one or more coherent agents configured to access the plurality of memories, and wherein the plurality of systems enforce coherency across the plurality of systems for at least some accesses. At least one of the plurality of systems is coupled to the switch interface circuit separate from the interconnection of the plurality of systems. The switch interface circuit is configured to interface the apparatus to a switch fabric.
摘要翻译：一种装置包括多个存储器，多个系统和开关接口电路。多个系统中的每一个包括耦合到多个存储器中的相应一个的存储器控制器。另外，多个系统中的每一个耦合到多个系统中的至少一个系统。所述多个系统中的每一个还包括被配置为访问所述多个存储器的一个或多个相干代理，并且其中所述多个系统对所述多个系统执行至少一些访问的相干性。多个系统中的至少一个耦合到与多个系统的互连分离的开关接口电路。开关接口电路被配置为将设备连接到交换结构。

42. 发明授权

EP0976047B1 READ OPERATIONS IN MULTIPROCESSOR COMPUTER SYSTEM 失效
标题翻译： LESEOPERATIONEN在einem MULTIPROZESSORRECHNERSYSTEM
公开(公告)号：EP0976047B1
公开(公告)日：2002-12-11
申请号：EP98914979.4
申请日：1998-04-03
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： ARIMILLI, Ravi, Kumar , DODSON, John, Steven , KAISER, John, Michael , LEWIS, Jerry, Don
IPC分类号： G06F12/08
CPC分类号： G06F12/0831
摘要： A method of improving memory latency associated with a read-type operation in a multiprocessor computer system is disclosed. After a value (data or instruction) is loaded from system memory into at least two caches, the caches are marked as containing shared, unmodified copies of the value and, when a requesting processing unit issues a message indicating that it desires to read the value, a given one of the caches transmits a response indicating that the given cache can source the value. The response is transmitted in response to the cache snooping the message from an interconnect which is connected to the requesting processing unit. The response is detected by system logic and forwarded from the system logic to the requesting processing unit. The cache then sources the value to an interconnect which is connected to the requesting processing unit. The system memory detects the message and would normally source the value, but the response informs the memory device that the value is to be sourced by the cache instead. Since the cache latency can be much less than the memory latency, the read performance can be substantially improved with this new protocol.

43. 发明公开

EP1163587A1 EINRICHTUNG ZUR ERHÖHUNG DER LEISTUNGSFÄHIGKEIT VON PROZESSORSYSTEMEN 审中-公开
标题翻译：设备技术提高处理器系统的效率
公开(公告)号：EP1163587A1
公开(公告)日：2001-12-19
申请号：EP00908968.1
申请日：2000-02-01
申请人： Fujitsu Siemens Computers GmbH
发明人： STOESS, Annie , SCHACHTNER, Johann , ZIEMANN, Wolfgang
IPC分类号： G06F12/08
CPC分类号： G06F12/0811 , G06F12/0831
摘要： The aim of the invention is to increase the capacity of processor systems consisting of a large number of individual processors using the MESI state model to maintain the cache coherence inside the processor system. To this end, more states are added to the MESI state model, which is otherwise limited to four states. In this way, the state situations inside the processor system can be handled in a more differentiated manner and unnecessary bus accesses can be avoided. The processing capacity which comes available as a result can be used to increase the capacity of the system.

44. 发明授权

EP0750258B1 Computer system with memory state recovery 失效
标题翻译：与存储器状态恢复计算机系统
公开(公告)号：EP0750258B1
公开(公告)日：2001-10-10
申请号：EP96109771.4
申请日：1996-06-18
申请人： KABUSHIKI KAISHA TOSHIBA
发明人： Masubuchi, Yoshio, c/o Intellectual Property Div.,
IPC分类号： G06F11/14 , G06F12/08
CPC分类号： G06F11/1407 , G06F12/0831

45. 发明授权

EP0497054B1 Apparatus and method for a synchronous, high speed, packet-switched bus 失效
标题翻译：装置和同步速度的方法，包交换总线
公开(公告)号：EP0497054B1
公开(公告)日：2001-09-19
申请号：EP91311835.2
申请日：1991-12-19
申请人： SUN MICROSYSTEMS, INC. , XEROX CORPORATION
发明人： Sindhu, Pradeep S , Liencres, Bjorn , Cruz-Rios, Jorge , Lee, Douglas B , Chang, Jung-Herng , Frailong, Jean-Marc
IPC分类号： G06F13/36 , G06F12/08
CPC分类号： G06F12/0831 , G06F12/1027 , G06F13/364 , G06F2212/682

46. 发明授权

EP0553338B1 HIGH-PERFORMANCE DYNAMIC MEMORY SYSTEM 有权转让
标题翻译：动态高性能的存储系统
公开(公告)号：EP0553338B1
公开(公告)日：1999-10-13
申请号：EP92918430.7
申请日：1992-08-14
申请人： CYPRESS SEMICONDUCTOR CORP.
发明人： LIEBERMAN, Donald, A. , NEMEC, John, J.
IPC分类号： G06F13/28 , G06F13/16
CPC分类号： G06F11/1016 , G06F11/1008 , G06F11/1044 , G06F12/0831 , G06F13/1673 , G06F13/1689 , G06F13/1694 , G06F13/28
摘要： A memory system includes a main memory and a memory controller. The main memory includes at least one block which has a plurality of banks. The memory controller includes a plurality of data channels each of which can access at least one bank in the main memory. Each data channel comprises a write first-in-first-out (FIFO) buffer for efficiently supporting cache purge operations and normal write operations, and a reflective write FIFO buffer for efficiently supporting coherent read with simultaneous cache copyback operations. The memory controller selects the proper FIFO or FIFOs depending on the type of data transaction, and selects the proper channel or channels depending on the system bus size, the data transaction size, and the status of the FIFO(s). The memory system can efficiently support data transactions having different data lengths or sizes from a byte to a long burst, and the timing resolution of the memory is enhanced regardless of the bus clock frequency. During burst transactions, the channels can run in an alternating fashion. During reads, the data is error-checked before being output to the system bus. The memory system can support different bus and processor systems and different data transactions in a highly efficient manner.

47. 发明公开

EP0942376A1 Method and system for pre-fetch cache interrogation using snoop port 审中-公开
标题翻译： Verfahren und System zur Cachespeicher-Vorausholungsabfragung unter Verwendung eines Snoptors
公开(公告)号：EP0942376A1
公开(公告)日：1999-09-15
申请号：EP99301537.9
申请日：1999-03-02
申请人： International Business Machines Corporation
发明人： Chan, Kin Shing , Hicks, Dwain Alan , Liu, Peichun Peter , Mayfield, Michael John , Tung, Shin Hsiung Stephen
IPC分类号： G06F12/08
CPC分类号： G06F12/0862 , G06F12/0831 , G06F12/1054
摘要： An interleaved data cache array which is divided into two subarrays is provided for utilization within a data processing system. Each subarray includes a plurality of cache lines wherein each cache line includes a selected block of data, a parity field, a content addressable field containing a portion of an effective address (ECAM) for the selected block of data, a second content addressable field contains a real address (RCAM) for the selected block of data and a data status field. Separate effective address ports (EA) and a real address port (RA) permit parallel access to the cache without conflict in separate subarrays and a subarray arbitration logic circuit is provided for attempted simultaneous access of a single subarray by both the effective address port (EA) and the real address port (RA). A normal word line is provided and activated by either the effective address port or the real address port through the subarray arbitration. An existing Real Address (RA) cache snoop port is used to check whether a pre-fetching stream's line access is a true cache hit or not. The snoop read access uses a (33-bit) real address to access the data cache without occupying a data port during testing of the pre-fetching stream hits. Therefore, the two Effective Address (EA) accesses and a RCAM snoop access can access the data cache simultaneously thereby increasing pre-fetching performance.
摘要翻译：提供分割成两个子阵列的交错数据高速缓存阵列用于数据处理系统内的利用。每个子阵列包括多个高速缓存行，其中每个高速缓存线包括所选择的数据块，奇偶校验字段，包含用于所选择的数据块的有效地址（ECAM）的一部分的内容可寻址字段，第二内容可寻址字段包含用于所选数据块的实际地址（RCAM）和数据状态字段。分离的有效地址端口（EA）和实际地址端口（RA）允许并行访问高速缓存，而不会在单独的子阵列中发生冲突，并提供子阵列仲裁逻辑电路，用于通过有效地址端口（EA）同时访问单个子阵列）和实际地址端口（RA）。正常字线由有效地址端口或实地址端口通过子阵列仲裁提供和激活。现有的实时地址（RA）缓存侦听端口用于检查预取流的线路访问是否是真正的缓存命中。在测试预取流命中期间，窥探读取访问使用（33位）真实地址访问数据高速缓存，而不占用数据端口。因此，两个有效地址（EA）访问和RCAM侦听访问可以同时访问数据高速缓存，从而增加预取性能。

48. 发明公开

EP0882265A1 APPARATUS AND METHOD FOR SIGNAL HANDLING ON GTL-TYPE BUSES 失效
标题翻译：装置及方法GTL型客车SIGNAL PROCESSING
公开(公告)号：EP0882265A1
公开(公告)日：1998-12-09
申请号：EP97907688.0
申请日：1997-02-19
申请人： Intergraph Corporation
发明人： BOECKMANN, Eduard, F. , BRETHOUR, Vern , SAMIEE, Vahid
IPC分类号： G06F12 , G06F13 , H03K19
CPC分类号： H03K19/018521 , G06F12/0822 , G06F12/0831 , G06F13/4022 , G06F13/4077 , H03K19/00361
摘要： An output driver for providing bus signals at a driver output in response to an input signal, the driver having a driver input signal responsive to the input signal, a supply voltage terminal and a ground terminal. The driver includes an improved clamping of an initially ON (i.e. high going) output pulse of the driver and adds an active pull-up function inside the integrated circuit that does not change the external circuit nor require additional functional external circuit connections.

49. 发明授权

EP0443755B1 Cache control system 失效
标题翻译：高速缓存控制系统
公开(公告)号：EP0443755B1
公开(公告)日：1998-12-09
申请号：EP91301062.5
申请日：1991-02-11
申请人： International Business Machines Corporation
发明人： Ohba, Nobuyuki , Shimizu, Shigenori
IPC分类号： G06F12/08
CPC分类号： G06F12/0831

50. 发明授权

EP0461926B1 Multilevel inclusion in multilevel cache hierarchies 失效
标题翻译：多级纳入多级高速缓存层次结构
公开(公告)号：EP0461926B1
公开(公告)日：1998-09-02
申请号：EP91305422.7
申请日：1991-06-14
申请人： Compaq Computer Corporation
发明人： Tipley, Roger E.
IPC分类号： G06F12/08
CPC分类号： G06F12/0811 , G06F12/0831

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式