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1. 发明公开

EP0443755A3 Cache control system 失效
标题翻译：缓存控制系统
公开(公告)号：EP0443755A3
公开(公告)日：1992-08-19
申请号：EP91301062.5
申请日：1991-02-11
申请人： International Business Machines Corporation
发明人： Ohba, Nobuyuki , Shimizu, Shigenori
IPC分类号： G06F12/08
CPC分类号： G06F12/0831
摘要： Cache control system for a private cache in a multiprocessor data processing system comprising a plurality of processors each connected to a shared bus via similar private caches, the cache control system co-operating with similar cache control systems provided for other private caches in the data processing system, the cache control system comprising: a controller for monitoring signals on the shared bus and, when data shared between ones of the processors is modified in the cache, for performing one of two or more types of data consistency procedures for the shared data; and means for determining the relative likelihood of access to the shared data by the processor corresponding to the private cache and other processors in the system, the type of data consistency procedure performed by the controller being dependent on the results of the determination.

2. 发明公开

EP0339782A2 Shared bus data processing systems 失效
标题翻译：巴西公共汽车公司（Datenverarbeitungssystem mit gemeinsamen Bus）。
公开(公告)号：EP0339782A2
公开(公告)日：1989-11-02
申请号：EP89302579.1
申请日：1989-03-16
申请人： International Business Machines Corporation
发明人： Ohba, Nobuyuki
IPC分类号： G06F13/36 , G06F13/374
CPC分类号： G06F13/374
摘要： A shared bus data processing system in which a plurality of potential bus masters can contend for time slot ownership on the shared bus on a priority basis is disclosed, wherein the current priority of each master is determined by comparing a count, adjusted monotonically in synchronism with the available time slots, is compared with one of a pair of stored boundary values for that master and, if that master is contending, is the priority value for that master if the current count is found to lie within the comparison boundary value, else is deemed to be the other stored boundary value. The stored boundary values and the initial count for each potential bus master are all programmable whereby "round robin" priority is obtainable by setting the stored boundary difference equal to the number of potential bus masters in the round robin and the initial counts to lie within the boundary difference and to be representative of the position within the round robin priority order of the particular potential bus master to which relates and fixed priority is obtainable by setting the two stored boundary values for a potential bus master to be equal.
摘要翻译：公开了一种共享总线数据处理系统，其中多个潜在总线主机可优先在共享总线上竞争时隙所有权，其中每个主机的当前优先级通过将与单独调整的计数进行同步调整将可用的时隙与该主机的一对存储的边界值中的一个进行比较，并且如果该主机正在竞争，则如果发现当前计数位于比较边界值内，则该主机的优先级值为否，否则为被视为另一个存储的边界值。存储的边界值和每个潜在总线主机的初始计数都是可编程的，通过将存储的边界差设置为等于循环中的潜在总线主机的数量，并且初始计数位于并且通过将潜在总线主机的两个存储的边界值设置为相等，可以获得与所关联的特定潜在总线主机的循环优先顺序中的位置和固定优先级的位置。

3. 发明公开

EP0339782A3 Shared bus data processing systems 失效
标题翻译：共享总线数据处理系统
公开(公告)号：EP0339782A3
公开(公告)日：1991-08-14
申请号：EP89302579.1
申请日：1989-03-16
申请人： International Business Machines Corporation
发明人： Ohba, Nobuyuki
IPC分类号： G06F13/36 , G06F13/374
CPC分类号： G06F13/374
摘要： A shared bus data processing system in which a plurality of potential bus masters can contend for time slot ownership on the shared bus on a priority basis is disclosed, wherein the current priority of each master is determined by comparing a count, adjusted monotonically in synchronism with the available time slots, is compared with one of a pair of stored boundary values for that master and, if that master is contending, is the priority value for that master if the current count is found to lie within the comparison boundary value, else is deemed to be the other stored boundary value. The stored boundary values and the initial count for each potential bus master are all programmable whereby "round robin" priority is obtainable by setting the stored boundary difference equal to the number of potential bus masters in the round robin and the initial counts to lie within the boundary difference and to be representative of the position within the round robin priority order of the particular potential bus master to which relates and fixed priority is obtainable by setting the two stored boundary values for a potential bus master to be equal.

4. 发明授权

EP0443755B1 Cache control system 失效
标题翻译：高速缓存控制系统
公开(公告)号：EP0443755B1
公开(公告)日：1998-12-09
申请号：EP91301062.5
申请日：1991-02-11
申请人： International Business Machines Corporation
发明人： Ohba, Nobuyuki , Shimizu, Shigenori
IPC分类号： G06F12/08
CPC分类号： G06F12/0831

5. 发明授权

EP0339782B1 Shared bus data processing systems 失效
标题翻译：一种数据处理系统具有共享总线。
公开(公告)号：EP0339782B1
公开(公告)日：1995-05-24
申请号：EP89302579.1
申请日：1989-03-16
申请人： International Business Machines Corporation
发明人： Ohba, Nobuyuki
IPC分类号： G06F13/36 , G06F13/374
CPC分类号： G06F13/374

6. 发明公开

EP0443755A2 Cache control system 失效
标题翻译：缓存Steuerungsanordnung。
公开(公告)号：EP0443755A2
公开(公告)日：1991-08-28
申请号：EP91301062.5
申请日：1991-02-11
申请人： International Business Machines Corporation
发明人： Ohba, Nobuyuki , Shimizu, Shigenori
IPC分类号： G06F12/08
CPC分类号： G06F12/0831
摘要： Cache control system for a private cache in a multiprocessor data processing system comprising a plurality of processors each connected to a shared bus via similar private caches, the cache control system co-operating with similar cache control systems provided for other private caches in the data processing system, the cache control system comprising: a controller for monitoring signals on the shared bus and, when data shared between ones of the processors is modified in the cache, for performing one of two or more types of data consistency procedures for the shared data; and means for determining the relative likelihood of access to the shared data by the processor corresponding to the private cache and other processors in the system, the type of data consistency procedure performed by the controller being dependent on the results of the determination.
摘要翻译：用于多处理器数据处理系统中的专用高速缓存的高速缓存控制系统，包括多个处理器，每个处理器通过类似的私有高速缓存连接到共享总线，该高速缓存控制系统与数据处理中的其他专用高速缓存提供的类似高速缓存控制系统系统，所述高速缓存控制系统包括：用于监视所述共享总线上的信号的控制器，以及当所述处理器中的一个处理器之间共享的数据在所述高速缓存中被修改时，用于执行所述共享数据的两种或多种类型的数据一致性过程中的一种; 以及用于确定由所述处理器对应于所述系统中的所述专用高速缓存和其他处理器的访问所述共享数据的相对可能性的方法，所述控制器执行的数据一致性过程的类型取决于所述确定的结果。

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