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41. 发明授权

EP0297518B1 Programmable read only memory with means for discharging bit line before program verifying operation 失效
标题翻译：可程序性读取操作之前，只能读取释放位线的记忆
公开(公告)号：EP0297518B1
公开(公告)日：1992-11-04
申请号：EP88110322.0
申请日：1988-06-28
申请人： NEC CORPORATION
发明人： Kobatake, Hiroyuki
IPC分类号： G11C29/00 , G11C17/00 , G11C16/00
CPC分类号： G11C29/38

42. 发明公开

EP0458518A1 Voltage divider for high-speed high-precision signal converting unit 失效
标题翻译：用于高速高精度信号转换单元的分压器
公开(公告)号：EP0458518A1
公开(公告)日：1991-11-27
申请号：EP91304344.4
申请日：1991-05-15
申请人： NEC CORPORATION
发明人： Kobatake, Hiroyuki
IPC分类号： H01L21/76
CPC分类号： H01L27/0218 , H01L27/0629
摘要： A voltage divider comprises a string of resistive elements (RN0 to RNn) implemented by an elongated n-type impurity region (14) formed in a lightly doped p-type semiconductor substrate (11), and n-channel type switching transistors (QN1 to QNn) with a short channel length formed in a heavily doped p-type well (12) in the semiconductor substrate and associated with the resistive elements for coupling one of the associated resistive elements to an output node (OUT). The lightly doped semiconductor substrate (11) decreases parasitic capacitance coupled to the elongated n-type impurity region (14) so that the string of the resistive elements is improved in propagation speed and bias dependency.
摘要翻译：分压器包括由形成于轻掺杂p型半导体衬底（11）中的细长n型杂质区（14）实现的一串电阻元件（RN0至RNn），以及n沟道型开关晶体管（QN1至 QNn），具有在半导体衬底中的重掺杂p型阱（12）中形成的短沟道长度，并且与用于将相关联的电阻元件中的一个耦合到输出节点（OUT）的电阻元件相关联。轻掺杂半导体衬底（11）减小耦合到细长n型杂质区域（14）的寄生电容，使得电阻元件串在传播速度和偏置依赖性方面得到改善。

43. 发明公开

EP0317939A3 Input circuit incorporated in a semiconductor device 失效
标题翻译：在半导体器件中并入的输入电路
公开(公告)号：EP0317939A3
公开(公告)日：1991-04-24
申请号：EP88119361.9
申请日：1988-11-21
申请人： NEC CORPORATION
发明人： Kobatake, Hiroyuki
IPC分类号： G11C5/06 , G11C16/06
CPC分类号： G11C5/066 , G11C16/06 , G11C16/10 , G11C16/12
摘要： An input circuit incorporated in a semiconductor device is provided in association with a multi-purpose input terminal (15) which is shared by first and second input signals (OE with over-bar/Vpp) different in voltage level from each other, and the input circuit comprises an input buffer circuit (25) for storing the first input signal, a series combination of a first field effect transistor (28), an intermediate node (N1) and a second field effect transistor (30) coupled between the multi-purpose input terminal and an internal circuit (12) supplied with the second input signal, a resister (29) coupled between a source of constant voltage (Vcc) and the intermediate node, a first control circuit (23) producing a first gate control signal supplied to a gate electrode of the second field effect transistor, and a second control circuit (26/40) capable of detecting the second input signal and producing a second gate control signal supplied to a gate electrode of the first field effect transistor, so that the second field effect transistor keeps off even if the first field effect transistor undesirable turns on.

44. 发明公开

EP0317939A2 Input circuit incorporated in a semiconductor device 失效
标题翻译： Eingangsschaltung，死在eine Halbleiteranlage eingegliedert ist。
公开(公告)号：EP0317939A2
公开(公告)日：1989-05-31
申请号：EP88119361.9
申请日：1988-11-21
申请人： NEC CORPORATION
发明人： Kobatake, Hiroyuki
IPC分类号： G11C5/06 , G11C16/06
CPC分类号： G11C5/066 , G11C16/06 , G11C16/10 , G11C16/12
摘要： An input circuit incorporated in a semiconductor device is provided in association with a multi-purpose input terminal (15) which is shared by first and second input signals (OE with over-bar/Vpp) different in voltage level from each other, and the input circuit comprises an input buffer circuit (25) for storing the first input signal, a series combination of a first field effect transistor (28), an intermediate node (N1) and a second field effect transistor (30) coupled between the multi-purpose input terminal and an internal circuit (12) supplied with the second input signal, a resister (29) coupled between a source of constant voltage (Vcc) and the intermediate node, a first control circuit (23) producing a first gate control signal supplied to a gate electrode of the second field effect transistor, and a second control circuit (26/40) capable of detecting the second input signal and producing a second gate control signal supplied to a gate electrode of the first field effect transistor, so that the second field effect transistor keeps off even if the first field effect transistor undesirable turns on.
摘要翻译：与多个用途的输入端子（15）相关联地提供一个结合在半导体器件中的输入电路，该多用途输入端子（15）由电压电平彼此不同的第一和第二输入信号（具有超棒/ Vpp的OE）共享，输入电路包括用于存储第一输入信号的输入缓冲电路（25），第一场效应晶体管（28），中间节点（N1）和第二场效应晶体管（30）的串联组合，提供第二输入信号的内部电路（12），耦合在恒定电压源（Vcc）和中间节点之间的电阻（29），产生第一栅极控制信号的第一控制电路（23）提供给第二场效应晶体管的栅电极，以及能够检测第二输入信号并产生提供给第一场效应晶体管的栅极的第二栅极控制信号的第二控制电路（26/40）使得第二场效应晶体管即使第一场效应晶体管不期望地导通而保持关断。

45. 发明公开

EP0297518A1 Programmable read only memory with means for discharging bit line before program verifying operation 失效
标题翻译：可编程只读存储器装置，用于将验证编程之前放电位线。
公开(公告)号：EP0297518A1
公开(公告)日：1989-01-04
申请号：EP88110322.0
申请日：1988-06-28
申请人： NEC CORPORATION
发明人： Kobatake, Hiroyuki
IPC分类号： G11C29/00 , G11C17/00 , G11C16/00
CPC分类号： G11C29/38
摘要： A semiconductor memory (1) in which each of memory cells includes a memory transistor (QM) having a control gate connected to a word line (WO), a floating gate and a drain-source path connected to a bit line (BO), is disclosed. In a data programming operation mode, a programming voltage (Vpp) is applied via the word and bit lines (WO, BO) to the control gate and the drain-source path of the memory transistor to inject carriers into the floating gate thereof. In order to detect whether or not the memory transistor (QM) is well programmed, a program verifying operation is carried out successively. To this end, the bit line (BO) is discharged to the low level and the word line (WO) is then supplied with a reading-out voltage. If the data programming is insufficient, the memory transistor (QM) is turned ON by the reading-out voltage, so that the bit line (BO) is held at a level near the low level. On the other hand, in case where the memory transistor (QM) is well programmed, it is not turned ON by the reading-out, so that the bit line (BO) is charged.
摘要翻译：一种半导体存储器（1），其中每个存储单元包括具有连接到字线的控制栅极的存储晶体管（QM）（WO），浮置栅极和连接于位线（BO）的漏极 - 源极路径，是游离缺失盘。在数据编程操作模式中，将编程电压（Vpp）为通过字线和位线（WO，BO）的控制栅极和其载流子注入到浮置栅极的存储晶体管的漏 - 源路径的应用。为了检测存储晶体管（QM）是否被很好编程，编程验证手术相继进行。为此，与位线（BO）被排出到低电平，并且该字线（WO），然后用一个读出电压。如果数据编程不足时，存储器晶体管（QM）由读出电压导通，所以做了位线（BO）在接近低电平的电平被保持。在另一方面，在存储晶体管（QM）是公编程的情况下，它没有被读出导通，所以做了位线（BO）被充电。

46. 发明公开

EP0174736A1 Circuit for detecting level of input voltage 失效
标题翻译：电路，用于检测输入电压的电平。
公开(公告)号：EP0174736A1
公开(公告)日：1986-03-19
申请号：EP85305677.8
申请日：1985-08-09
申请人： NEC CORPORATION
发明人： Kobatake, Hiroyuki
IPC分类号： G01R19/165 , H03K5/24
CPC分类号： H03K5/2472 , G01R19/16519
摘要： A circuit for detecting the level of an input voltage is disclosed, in which the input voltage is converted into a current and this current is compared with a reference current obtained by converting a reference voltage. To accomplish such circuit functions, this level detection circuit comprises means for converting the input voltage into a first current, means for converting the reference voltage into a second current, means for producing a third current relative to the first current, means for producing a fourth current relative to the second current, and means for combining the third and fourth current. A detection output terminal is coupled to the combining means.

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