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1. 发明公开

EP0942432A2 Non-volatile semiconductor storage device 有权
标题翻译：非易失性半导体存储装置
公开(公告)号：EP0942432A2
公开(公告)日：1999-09-15
申请号：EP99103972.8
申请日：1999-03-10
申请人： NEC CORPORATION
发明人： Kobatake, Hiroyuki
IPC分类号： G11C16/06
CPC分类号： G11C16/30 , G11C16/10
摘要： Disclosed herein is a non-volatile semiconductor storage device having a plurality of non-volatile memory cells formed by cell transistors (CTr1) in which a first voltage is applied to a word line (WL) through an address selection circuit (11) and a second voltage lower than the first voltage is applied to the transistors (STr1 and STr2) through a selection line (SL) and/or a bit line (BL). The voltage applied to the transistors (CTr1, STr1 and STr2) is lower than that conventionally employed. Accordingly, a withstand voltage of the transistor (CTr1, STr1 and STr2) can be reduced to decrease the occupied area of the transistors (CTr1, STr1 and STr2) and the like to realize higher integration.
摘要翻译：本发明公开了一种非易失性半导体存储装置，其具有由单元晶体管（CTr1）形成的多个非易失性存储单元，其中第一电压通过地址选择电路（11）施加到字线（WL）通过选择线（SL）和/或位线（BL）将低于第一电压的第二电压施加到晶体管（STr1和STr2）。施加到晶体管（CTr1，STr1和STr2）的电压低于常规使用的电压。因此，可以降低晶体管（CTr1，STr1和STr2）的耐受电压以减小晶体管（CTr1，STr1和STr2）等的占用面积以实现更高的集成度。

2. 发明公开

EP0833345A2 Non-volatile semiconductor memory device 失效
标题翻译： NichtflüchtigeHalbleiterspeicheranordnung
公开(公告)号：EP0833345A2
公开(公告)日：1998-04-01
申请号：EP97116877.8
申请日：1997-09-29
申请人： NEC Corporation
发明人： Kobatake, Hiroyuki
IPC分类号： G11C16/06
CPC分类号： G11C16/16 , G11C11/005
摘要： A non-volatile semiconductor memory device comprises an EEPROM array section (16) and a flash memory array section (17) formed on a single chip. The EEPROM memory array section (16) is subjected to a bite-by-bite mode erasure whereas the flash memory array section (17) is subjected to a batch mode erasure. The floating gate (34) of the EEPROM array section (16) has a large area than the floating gate (34) of the flash memory array section (17).
摘要翻译：非易失性半导体存储器件包括形成在单个芯片上的EEPROM阵列部分（16）和闪存阵列部分（17）。 EEPROM存储器阵列部分（16）经受咬咬模式擦除，而闪速存储器阵列部分（17）经受批次模式擦除。 EEPROM阵列部分（16）的浮动栅极（34）具有比闪存阵列部分（17）的浮动栅极（34）大的面积。

3. 发明授权

EP0317939B1 Input circuit incorporated in a semiconductor device 失效
标题翻译：输入电路，其被在半导体厂并入。
公开(公告)号：EP0317939B1
公开(公告)日：1994-03-09
申请号：EP88119361.9
申请日：1988-11-21
申请人： NEC CORPORATION
发明人： Kobatake, Hiroyuki
IPC分类号： G11C5/06 , G11C16/06
CPC分类号： G11C5/066 , G11C16/06 , G11C16/10 , G11C16/12

4. 发明公开

EP0348893A2 High speed non-volatile memory device 失效
标题翻译： NichtflüchtigeHochgeschwindigkeitsspeichervorrichtung。
公开(公告)号：EP0348893A2
公开(公告)日：1990-01-03
申请号：EP89111676.6
申请日：1989-06-27
申请人： NEC CORPORATION
发明人： Kobatake, Hiroyuki
IPC分类号： G11C17/00
CPC分类号： G11C17/12 , G11C16/24
摘要： A discharging circuit (26) is incororpated in a read only memory device according to the present invention for discharging the non selected bit lines (DY1 to DY3) to the ground level upon reading out operation from the accessed read only memory cell (M00), and, for this reason, the selected bit line (DY0) is rapidly changed in voltage level for propagating the data bit to a sense amplifier circuit ((27) even if a large capacitance (C01) is coupled between the adjacent bit lines.
摘要翻译：放电电路（26）被并入根据本发明的只读存储器件中，用于在从所访问的只读存储器单元（M00）读出操作时将未选择的位线（DY1至DY3）放电到地电平，并且为此，即使在相邻位线之间耦合大电容（C01），所选择的位线（DY0）在用于将数据位传播到读出放大器电路（（27））的电压电平中迅速改变。

5. 发明公开

EP0189594A3 Non-volatile semiconductor memory device 失效
标题翻译：非易失性半导体存储器件
公开(公告)号：EP0189594A3
公开(公告)日：1988-12-07
申请号：EP85116579
申请日：1985-12-27
申请人： NEC CORPORATION
发明人： Kobatake, Hiroyuki
IPC分类号： G11C17/00 , G11C08/00
CPC分类号： G11C16/08 , G11C8/10
摘要： A non-volatile semiconductor memory device has a plurality of memory cells which are coupled to a plurality of row or column lines through which a high voltage is supplied in a data write operation and a plurality of switching circuits, each of which is coupled to the corresponding row or column line. In a data write operation, only one of switching circuits is turned on to supply the high voltage to only one row or column lines coupled to a memory cell in which a data is to be written.

6. 发明公开

EP0942432A3 Non-volatile semiconductor storage device 有权
公开(公告)号：EP0942432A3
公开(公告)日：2000-06-07
申请号：EP99103972.8
申请日：1999-03-10
申请人： NEC CORPORATION
发明人： Kobatake, Hiroyuki
IPC分类号： G11C16/30 , G11C16/12 , G11C16/10
CPC分类号： G11C16/30 , G11C16/10
摘要： Disclosed herein is a non-volatile semiconductor storage device having a plurality of non-volatile memory cells formed by cell transistors (CTr1) in which a first voltage is applied to a word line (WL) through an address selection circuit (11) and a second voltage lower than the first voltage is applied to the transistors (STr1 and STr2) through a selection line (SL) and/or a bit line (BL). The voltage applied to the transistors (CTr1, STr1 and STr2) is lower than that conventionally employed. Accordingly, a withstand voltage of the transistor (CTr1, STr1 and STr2) can be reduced to decrease the occupied area of the transistors (CTr1, STr1 and STr2) and the like to realize higher integration.

7. 发明公开

EP0880180A1 Non-volatile semiconductor memory device with write circuit having a latch and a transfer gate 失效
标题翻译： Schreibschaltung mit Verriegelungschaltung undÜbertragungstransistorin einernichtflüchtigenSpeicherzellenanordnung
公开(公告)号：EP0880180A1
公开(公告)日：1998-11-25
申请号：EP98109119.2
申请日：1998-05-19
申请人： NEC CORPORATION
发明人： Kobatake, Hiroyuki
IPC分类号： H01L27/115 , G11C16/06
CPC分类号： G11C16/10
摘要： A non-volatile semiconductor memory device of the present invention has a write circuit and bit line coupled to the latch circuit. Write data is latched in a latch circuit. Output from the write circuit is sent to corresponding bit line by a transfer gate. During data write term, a write voltage is applied to the bit line when writing a "0" and zero volts is applied to the bit line when writing a "1". The bit line therefore is not left in a floating state when writing either a "0" or a "1". A rise in voltage potential of a bit line due to noise is prevented from occurring, thereby eliminating data writing errors.
摘要翻译：本发明的非易失性半导体存储器件具有耦合到锁存电路的写入电路和位线。写数据被锁存在锁存电路中。来自写入电路的输出通过传输门发送到相应的位线。在数据写入期间，当写入“0”时，写入电压被施加到位线，写入“1”时将零电压施加到位线。因此，当写入“0”或“1”时，位线不会处于浮动状态。由于噪声引起的位线的电压电位的上升被防止发生，从而消除数据写入错误。

8. 发明公开

EP0820102A2 Read-only semiconductor memory device 失效
标题翻译：只读与浮动栅极的半导体存储器件
公开(公告)号：EP0820102A2
公开(公告)日：1998-01-21
申请号：EP97112090.2
申请日：1997-07-15
申请人： NEC CORPORATION
发明人： Kobatake, Hiroyuki
IPC分类号： H01L27/115
CPC分类号： H01L27/115
摘要： An n-type drain diffusion layer (11), an n-type source diffusion layer (12) and an n-type control gate diffusion layer (14) are formed on the surface of a p-type semiconductor substrate (10). Furthermore, an n-type well (15) is connected to the control gate diffusion layer (14). A control gate electrode (54) of aluminum is connected to the well (15). An isolation oxide layer (17) is formed between the control gate electrode (54) and the control gate diffusion layer (14). On the other hand, a first insulation layer (19a,19b) is formed on the drain diffusion layer (11), the source diffusion layer (12) and the control gate diffusion layer (14). Also, a floating gate (13) is formed on the first insulation layer (19a, 19b). The upper portion and the side portion of the floating gate (13) are covered with a second insulation layer (20). The floating gate (13) is completely covered with a protective gate (18) via the second insulation layer (20). The end edge of the protective gate (18) opposes to the well (15) via the isolation oxide layer (17). Also, the drain diffusion layer (11) and the protective gate are (18) connected to each other to have the same potential.

9. 发明授权

EP0348895B1 Semiconductor memory device provided with low-noise power supply structure 失效
标题翻译：一种半导体存储器件，其装备有一个低噪声电源。
公开(公告)号：EP0348895B1
公开(公告)日：1995-05-17
申请号：EP89111678.2
申请日：1989-06-27
申请人： NEC CORPORATION
发明人： Kobatake, Hiroyuki
IPC分类号： G11C5/00 , G11C17/00
CPC分类号： G11C17/123 , G11C5/147 , G11C17/12

10. 发明公开

EP0501481A3 Current controller 失效
标题翻译：电流控制器
公开(公告)号：EP0501481A3
公开(公告)日：1993-03-17
申请号：EP92103374.2
申请日：1992-02-27
申请人： NEC CORPORATION
发明人： Kobatake, Hiroyuki
IPC分类号： H03K17/16 , H03K17/687 , G11B5/09 , G11B5/02 , G11B20/10
CPC分类号： H03K17/163 , G11B5/09
摘要： A current controller (36) includes a first MOSFET of P type (40) connected at a drain to a first node (42), at a gate to the input terminal (IN) and at a source to power supply (VCC), a second MOSFET of N type (44) connected at a drain to the first node (42) via a first resistor (45), at a gate to the input terminal (IN) and at a source to ground (GND), a third MOSFET of N type (46) connected at a drain to the output terminal (OUT), at a gate to the first node (42) via a second resistor (48) and at a source to ground (GND), and a capacitor (50) connected between the gate of the third MOSFET (46) and ground (GND). The first and second resistors (45,48) and the capacitor (50) are set so that the maximum changing rates of rising and falling currents supplied from the output terminal (OUT) through the third MOSFET (46) are equalized. Therefore, levels of low level data are equalized between the positive and negative sides.

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